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74LVTH16652 데이터시트 PDF




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부품번호 74LVTH16652 기능
기능 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
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74LVTH16652 데이터시트, 핀배열, 회로
January 2000
Revised January 2000
74LVTH16652
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVTH16652 consists of sixteen bus transceiver circuits
with D-type flip-flops, and control circuitry arranged for mul-
tiplexed transmission of data directly from the input bus or
from the internal registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. Data on the A or B bus will be clocked into the regis-
ters as the appropriate clock pin goes to the HIGH logic
level. Output Enable pins (OEAB, OEBA) are provided to
control the transceiver function (see Functional Descrip-
tion).
The LVTH16652 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceivers are designed for low-voltage (3.3V) VCC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16652 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 16652
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH16652MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16652MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS012024
www.fairchildsemi.com




74LVTH16652 pdf, 반도체, 판매, 대치품
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SABn, SBAn) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management functions that can be performed with the
LVTH16652.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPABn, CPBAn) regardless of
the Select or Output Enable Inputs. When SAB and SBA
are in the real time transfer mode, it is also possible to
store data without using the internal D flip-flops by simulta-
neously enabling OEABn and OEBAn. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
Real-Time Transfer
Bus B to Bus A
Storage
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
L L X X XL
Real-Time Transfer
Bus A to Bus B
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
X H
X XX
L X X
XX
 L H
XX
Transfer Storage
Data to A or B
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
H H X X LX
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1
H L H or L H or L H H
www.fairchildsemi.com
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74LVTH16652 전자부품, 판매, 대치품
AC Electrical Characteristics
TA = −40°C to +85°C
Symbol
Parameter
CL = 50 pF, RL = 500
VCC = 3.3V ± 0.3V
VCC = 2.7V
Units
Min Max Min Max
fMAX
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
Maximum Clock Frequency
Propagation Delay
CPAB or CPBA to A or B
Propagation Delay
Data to A or B
Propagation Delay
SBA or SAB to A or B
Output Enable Time
OE to A
150 150 MHz
1.3 4.8 1.3 5.4
ns
1.3 5.1 1.3 5.6
1.0 4.5 1.0 5.1
ns
1.0 4.4 1.0 4.7
1.0 4.9 1.0 5.5
ns
1.0 4.8 1.0 5.4
1.0 4.9 1.0 5.8
ns
1.0 4.8 1.0 5.8
tPLZ
tPHZ
Output Disable Time
OE to A
1.6 5.6 1.6 6.1
ns
2.0 5.4 2.0 6.1
tPZL
tPZH
Output Enable Time
OE to B
1.3 5.0 1.3 5.4
ns
1.3 4.8 1.3 5.4
tPLZ
tPHZ
Output Disable Time
OE to B
1.3 5.5 1.3 6.2
ns
1.3 5.6 1.3 6.3
tS Setup Time
A or B before CPAB or CPBA, Data HIGH 1.2
1.5
ns
A or B before CPAB or CPBA, Data LOW 2.0
2.8
tH Hold Time
A or B before CPAB or CPBA, Data HIGH
A or B before CPAB or CPBA, Data LOW
0.5
0.5
0.0
0.5
ns
tW Pulse Width
CPAB or CPBA HIGH or LOW 3.3 3.3 ns
tOSHL
tOSLH
Output to Output Skew (Note 9)
1.0 1.0
ns
1.0 1.0
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = Open, VI = 0V or VCC
CI/O Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
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관련 데이터시트

부품번호상세설명 및 기능제조사
74LVTH16652

Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor
74LVTH16652MEA

Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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