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74LVTH273 데이터시트 PDF




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부품번호 74LVTH273 기능
기능 Low Voltage Octal D-Type Flip-Flop with Clear
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74LVTH273 데이터시트, 핀배열, 회로
July 1999
Revised July 1999
74LVTH273
Low Voltage Octal D-Type Flip-Flop with Clear
General Description
The LVTH273 is a high-speed, low-power positive-edge-
triggered octal D-type flip-flop featuring separate D-type
inputs for each flip-flop. A buffered Clock (CP) and Clear
(CLR) are common to all flip-flops.
The state of each D-type input, one setup time before the
positive clock transition, is transferred to the corresponding
flip-flop’s output.
The LVTH273 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVTH273 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold on the data inputs eliminate the need for
external pull-up resistors to hold unused inputs
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 273
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVTH273WM
74LVTH273SJ
74LVTH273MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS500100
www.fairchildsemi.com




74LVTH273 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Note 3: All typical values are at VCC = 3.3V, TA = 25°C.
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics (Note 7)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.8
Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 8: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Units
V
V
Conditions
CL = 50 pF,
RL = 500
(Note 8)
(Note 8)
Symbol
Parameter
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay
CP to On
tPHL Propagation Delay CLR to On
tW Pulse Duration
tS Setup Time
Data HIGH or LOW before CP
CLR HIGH before CP
tH Hold Time
Data HIGH or LOW after CP
Note 9: All typical values are at VCC = 3.3V, TA = 25°C.
Capacitance (Note 10)
TA = −40°C to +85°C
CL = 50 pF, RL = 500
VCC = 3.3V ± 0.3V
VCC = 2.7V
Min Typ Max Min Max
(Note 9)
150 150
1.7 4.9 1.7 5.5
1.9 4.8 1.9 5.1
1.6 4.8 1.6 5.4
3.3 3.3
2.3 2.7
2.3 2.7
00
Units
MHz
ns
ns
ns
ns
ns
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
Typical
3
6
Units
pF
pF
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74LVTH273

Low Voltage Octal D-Type Flip-Flop with Clear

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