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74LVTH374WM 데이터시트 PDF




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부품번호 74LVTH374WM 기능
기능 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
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74LVTH374WM 데이터시트, 핀배열, 회로
September 1999
Revised October 1999
74LVT374 • 74LVTH374
Low Voltage Octal D-Type Flip-Flop
with 3-STATE Outputs
General Description
The LVT374 and LVTH374 are high-speed, low-power
octal D-type flip-flops featuring separate D-type inputs for
each flip-flop and 3-STATE outputs for bus-oriented appli-
cations. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The LVTH374 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal flip-flops are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT374 and LVTH374
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bus-Hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH374),
also available without bushold feature (74LVT374).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 374
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
74LVT374WM
74LVT374SJ
74LVT374MTC
74LVTH374WM
74LVTH374SJ
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012016
www.fairchildsemi.com




74LVTH374WM pdf, 반도체, 판매, 대치품
DC Electrical Characteristics
Symbol
Parameter
VCC(V)
VIK
VIH
VIL
VOH
VOL
II(HOLD)
(Note 4)
II(OD)
(Note 4)
II
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Bushold Input Minimum Drive
2.7
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
2.7
2.7
3.0
3.0
3.0
3.0
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
3.0
3.6
3.6
3.6
IOFF
IPU/PD
IOZL
IOZH
IOZH+
ICCH
ICCL
ICCZ
ICCZ+
Power Off Leakage Current
Power up/down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
T A = −40°C to +85°C
Min Typ Max
(Note 3)
1.2
2.0
0.8
VCC 0.2
2.4
2.0
0.2
0.5
0.4
0.5
0.55
75
75
500
500
10
±1
5
1
±100
±100
5
5
10
0.19
5
0.19
0.19
Units
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
ICC
Increase in Power Supply Current
(Note 7)
3.6
0.2 mA
Note 3: All typical values are at VCC = 3.3V, TA = 25°C.
Note 4: Applies to Bushold versions only (74LVTH374).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
II = −18 mA
VO 0.1V or
VO VCC 0.1V
IOH = −100 µA
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
VI = 0.8V
VI = 2.0V
(Note 5)
(Note 6)
VI = 5.5V
VI = 0V or VCC
VI = 0V
VI = VCC
0V VI or VO 5.5V
VO = 0.5V to 3.0V
VI = GND or VCC
VO = 0.5V
VO = 3.0V
VCC < VO 5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
VCC VO 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V)
Min Typ Max
VOLP
VOLV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
3.3
3.3
0.8
0.8
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Units
V
V
Conditions
CL = 50 pF
RL = 500
(Note 9)
(Note 9)
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74LVTH374WM 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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74LVTH374WM

Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Fairchild Semiconductor
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