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Número de pieza | 74LVTH543WM | |
Descripción | Low Voltage Octal Registered Transceiver with 3-STATE Outputs | |
Fabricantes | Fairchild Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 74LVTH543WM (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
No Preview Available ! April 2000
Revised April 2000
74LVTH543
Low Voltage Octal Registered Transceiver
with 3-STATE Outputs
General Description
The LVTH543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow.
The LVTH543 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
This octal registered transceiver is designed for low-volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVTH543 is
fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 543
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVTH543WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH543MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CEAB, CEBA
A0–A7
B0–B7
Description
Output Enable Inputs
Latch Enable Inputs
Chip Enable Inputs
Side A Inputs or
3-STATE Outputs
Side B Inputs or
3-STATE Outputs
© 2000 Fairchild Semiconductor Corporation DS012448
www.fairchildsemi.com
1 page AC Electrical Characteristics
Symbol
Parameter
tPLH Propagation Delay
tPHL Data to Outputs
tPLH Propagation Delay
tPHL LE to A or B
tPZH Output Enable Time
tPZL OE to A or B
tPHZ Output Disable Time
tPLZ OE to A or B
tPZH Output Enable Time
tPZL CE to A or B
tPHZ Output Disable Time
tPLZ CE to A or B
tW Pulse Duration
LE LOW
TA = −40°C to +85°C
CL = 50 pF, RL = 500Ω
VCC = 3.3V ± 0.3V
VCC = 2.7V
Min Max Min Max
1.3 4.4 1.3 4.8
1.3 4.6 1.3 5.2
1.3 5.4 1.3 6.4
1.3 5.8 1.3 6.6
1.1 5.5 1.1 6.3
1.1 6.1 1.1 7.2
2.0 5.7 2.0 5.9
2.0 5.3 2.0 5.9
1.3 5.9 1.3 6.8
1.3 6.2 1.3 7.4
2.1 5.8 2.1 6.1
1.6 5.4 1.6 5.9
3.3 3.3
Units
ns
ns
ns
ns
ns
ns
ns
tS Setup Time
A or B before LE, Data HIGH
A or B before LE, Data LOW
A or B before CE, Data HIGH
0.4
1.0
0.2
0.4
1.5
0.2
ns
A or B before CE, Data LOW
0.7
1.2
tH Hold Time
A or B before LE, Data HIGH
A or B before LE, Data LOW
A or B before CE, Data HIGH
1.5
1.3
1.6
0.6
1.5
0.5
ns
A or B before CE, Data LOW
1.4
1.6
tOSHL
tOSLH
Output to Output Skew (Note 8)
1.0 1.0
ns
1.0 1.0
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 9)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
CI/O
Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 9: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet 74LVTH543WM.PDF ] |
Número de pieza | Descripción | Fabricantes |
74LVTH543WM | Low Voltage Octal Registered Transceiver with 3-STATE Outputs | Fairchild Semiconductor |
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