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74LVTH573MTC 데이터시트 PDF




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부품번호 74LVTH573MTC 기능
기능 Low Voltage Octal Transparent Latch with 3-STATE Outputs
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74LVTH573MTC 데이터시트, 핀배열, 회로
March 1999
Revised March 1999
74LVT573 • 74LVTH573
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT573 and LVTH573 consist of eight latches with 3-
STATE outputs for bus organized system applications. The
latches appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is low, the data satisfying the input
timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The LVTH573 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT573 and LVTH573
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH573), also
available without bushold feature (74LVT573).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 573
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVT573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
74LVT573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVT573MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVTH573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVTH573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide
74LVTH573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH573MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS012450.prf
www.fairchildsemi.com




74LVTH573MTC pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
IOZH
IOZH+
ICCH
ICCL
ICCZ
ICCZ+
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
VCC T A = −40°C to +85°C
Min Typ Max Units
(V) (Note 3)
3.6 5 µA
3.6 10 µA
3.6
0.19
mA
3.6 5 mA
3.6
0.19
mA
3.6
0.19
mA
ICC
Increase in Power Supply Current
(Note 7)
3.6
0.2 mA
Note 3: All typical values are at VCC = 3.3V, TA = 25°C.
Note 4: Applies to bushold versions only (74LVTH573).
Note 5: An external driver must source at least the specified current to switch from LOW to HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH to LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Conditions
VO = 3.0V
VCC < VO 5.5V
Outputs High
Outputs Low
Outputs Disabled
VCC VO 5.5V,
Outputs Disabled
One Input at VCC 0.6V
Other Inputs at VCC or GND
Dynamic Switching Characteristics (Note 8)
Symbol
Parameter
VCC TA = 25°C
(V) Min Typ
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.8
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.8
Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
Max
Units
V
V
Conditions
CL = 50 pF
RL = 500
(Note 9)
(Note 9)
AC Electrical Characteristics
TA = −40°C to +85°C
CL = 50 pF, RL = 500
Symbol
Parameter
VCC = 3.3V ±0.3V
VCC = 2.7V
Units
Min
Typ
(Note 10)
Max
Min
Max
tPHL Propagation Delay
tPLH
Dn to On
tPHL Propagation Delay
tPLH LE to On
tPZL Output Enable Time
tPZH
tPLZ Output Disable Time
tPHZ
tS Setup Time, Dn to LE
tH Hold Time, Dn to LE
tW LE Pulse Width
tOSHL
Output to Output Skew (Note 11)
tOSLH
Note 10: All typical values are at VCC = 3.3V, TA = 25°C.
1.5
1.5
1.9
1.9
1.5
1.5
2.0
2.0
0.7
1.5
3.0
4.4 1.5 4.9
ns
4.1 1.5 4.7
4.4 1.9 4.9
ns
4.4 1.9 5.0
5.1 1.5 6.6
ns
5.1 1.5 5.9
4.6 2.0 4.9
ns
4.9 2.0 5.5
0.6 ns
1.7 ns
3.0 ns
1.0 1.0
ns
1.0 1.0
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = Open, VI = 0V or VCC
COUT
Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
6
Units
pF
pF
www.fairchildsemi.com
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74LVTH573MTC 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA20
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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74LVTH573MTC

Low Voltage Octal Transparent Latch with 3-STATE Outputs

Fairchild Semiconductor
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