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74LVX125 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 74LVX125은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 74LVX125 자료 제공

부품번호 74LVX125 기능
기능 Low Voltage Quad Buffer with 3-STATE Outputs
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74LVX125 데이터시트, 핀배열, 회로
February 2008
74LVX125
Low Voltage Quad Buffer with 3-STATE Outputs
Features
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
General Description
The LVX125 contains four independent non-inverting
buffers with 3-STATE outputs. The inputs tolerate volt-
ages up to 7V allowing the interface of 5V systems to 3V
systems.
Ordering Information
Order
Number
74LVX125M
74LVX125SJ
74LVX125MTC
Package
Number
M14A
M14D
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
An
OEn
On
Description
Inputs
Output Enable Inputs
Outputs
©1994 Fairchild Semiconductor Corporation
74LVX125 Rev. 1.4.0
Truth Table
Inputs
OEn
L
L
H
An
L
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
Output
On
L
H
Z
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74LVX125 pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
tPLH, tPHL
Parameter
Propagation Delay
Time, Data to
Output
tPZH, tPZL Output Enable Time
tPHZ, tPLZ Output Disable
Time
tOSHL, tOSLH Output to Output
Skew(3)
VCC (V)
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3
Conditions
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF, RL = 1k
CL = 50pF, RL = 1k
CL = 15pF, RL = 1k
CL = 50pF, RL = 1k
CL = 50pF, RL = 1k
CL = 50pF, RL = 1k
CL = 50pF
TA = +25°C
Min. Typ. Max.
5.8 10.1
8.3 13.6
4.4 6.2
6.9 9.7
5.3 9.3
7.8 12.8
4.0 5.6
6.5 9.1
10.0 15.7
8.3 11.2
1.5
1.5
TA = –40°C
to +85°C
Min. Max. Units
1.0 13.5 ns
1.0 17.0
1.0 8.5
1.0 12.0
1.0 12.5 ns
1.0 16.0
1.0 7.5
1.0 11.0
1.0 19.0 ns
1.0 13.0
1.5 ns
1.5
Note:
3. Parameter guaranteed by design tOSLH = |tPLHm–tPLHn|, tOSHL = |tPHLm–tPHLn|
Capacitance
Symbol
Parameter
TA = +25°C
Min. Typ. Max.
TA = –40°C to
+85°C
Min. Max.
Units
CIN Input Capacitance
CPD Power Dissipation Capacitance(4)
4 10
14
10 pF
pF
Note:
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
Average operating current can be obtained by the eqation: ICC(opr.) = -C----P----D----×-4----V-(--p-C---e-C--r--,-×--b---f-i-I-tN--)---×-----I--C----C-
©1994 Fairchild Semiconductor Corporation
74LVX125 Rev. 1.4.0
4
www.fairchildsemi.com

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74LVX125 전자부품, 판매, 대치품
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
0.45
6.10
R0.09 min
12.00°TOP & BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1994 Fairchild Semiconductor Corporation
74LVX125 Rev. 1.4.0
7
www.fairchildsemi.com

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