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74LVX161284MTD 데이터시트 PDF




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부품번호 74LVX161284MTD 기능
기능 Low Voltage IEEE 161284 Translating Transceiver
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74LVX161284MTD 데이터시트, 핀배열, 회로
January 1999
Revised July 2000
74LVX161284
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in an
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (± 14 mA) and are connected to a
separate power supply pin (VCCcable) to allow these out-
puts to be driven by a higher supply voltage than the
A-side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCCcable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
s Translation capability allows outputs on the cable side to
interface with 5V signals
s All inputs have hysteresis to provide noise margin
s B and Y output resistance optimized to drive external
cable
s B and Y outputs in high impedance mode during power
down
s Inputs and outputs on cable side have internal pull-up
resistors
s Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
s Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number Package Number
Package Description
74LVX161284MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVX161284MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
HD High Drive Enable Input (Active HIGH)
DIR Direction Control Input
A1A8
B1B8
A9A13
Y9Y13
A14A17
C14C17
PLHIN
PLH
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
HLHIN
HLH
Host Logic HIGH Input
Host Logic HIGH Output
© 2000 Fairchild Semiconductor Corporation DS500202
www.fairchildsemi.com




74LVX161284MTD pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
VCC
(V)
VCCCable
(V)
TA = 0°C
TA = −40°C
to +70°C
to +85°C
Guaranteed Limits
Units
Conditions
VOL Maximum LOW An, HLH
Level Output
Voltage
Bn, Yn
Bn, Yn
PLH
PLH
RD
Maximum Output
B1B8, Y9Y13
Impedance
Minimum Output
Impedance
B1B8, Y9Y13
3.0 3.0
3.0 3.0
3.0 3.0
3.0 4.5
3.0 3.0
3.0 4.5
3.3 3.3
3.3 5.0
3.3 3.3
3.3 5.0
0.2
0.4
0.8
0.77
0.85
0.8
60
55
30
35
0.2
0.4
0.8
0.77
0.95
0.9
60
55
30
35
IOL = 50 µA
IOL = 4 mA
V IOL = 14 mA
IOL = 14 mA
IOL = 84 mA
IOL = 84 mA
(Note 5)(Note 7)
(Note 5)(Note 7)
RP
IIH
IIL
IOZH
IOZL
IOFF
Maximum Pull-Up
Resistance
Minimum Pull-Up
Resistance
Maximum Input
Current in
HIGH State
Maximum Input
Current in
LOW State
Maximum Output
Disable Current
(HIGH)
Maximum
Output Disable
Current (LOW)
Power Down
Output Leakage
B1B8, Y9Y13,
C14C17
B1B8, Y9Y13
C14C17
A9A13, PLHIN,
HD, DIR, HLHIN
C14C17
C14C17
A9A13, PLHIN,
HD, DIR, HLHIN
C14C17
C14C17
A1A8
B1B8
B1B8
A1A8
B1B8
B1B8
B1B8, Y9Y13,
PLH
3.3 3.3
3.3 5.0
3.3 3.3
3.3 5.0
3.6 3.6
3.6 3.6
3.6 5.5
3.6 3.6
3.6 3.6
3.6 5.5
3.6 3.6
3.6 3.6
3.6 5.5
3.6 3.6
3.6 3.6
3.6 5.5
0.0 0.0
1650
1650
1150
1150
1.0
50.0
100
1.0
3.5
5.0
20
50
100
20
3.5
5.0
100
1650
1650
1150
1150
1.0
50.0
100
1.0
3.5
5.0
20
50
100
20
3.5
5.0
100
VI = 3.6V
µA
VI = 3.6V
VI = 5.5V
µA VI = 0.0V
mA VI = 0.0V
mA VI = 0.0V
µA VO = 3.6V
µA VO = 3.6V
µA VO = 5.5V
µA VO = 0.0V
mA
mA
µA VO = 5.5V
IOFF
Power Down
Input Leakage
C14C17, HLHIN
0.0 0.0
100
100 µA VI = 5.5V
IOFFICC
IOFFICC2
ICC
Power Down
Leakage to VCC
Power Down Leakage
to VCCCable
Maximum Supply
Current
0.0 0.0
0.0 0.0
3.6 3.6
3.6 5.5
250
250
45
70
Note 5: Output impedance is measured with the output active LOW and active HIGH (HD = HIGH).
250 µA (Note 6)
250 µA (Note 6)
45 mA VI = VCC or GND
70 mA VI = VCC or GND
Note 6: Power-down leakage to VCC or VCCCable is tested by simultaneously forcing all pins on the cable-side (B1B8, Y9Y13, PLH, C14C17 and HLHIN)
to 5.5V and measuring the resulting ICC or ICCCable.
Note 7: This parameter is guaranteed but not tested, characterized only.
www.fairchildsemi.com
4

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74LVX161284MTD 전자부품, 판매, 대치품
AC Loading and Waveforms (Continued)
FIGURE 4. tSLEW HL Test Load and Waveforms
A1A8 to B1B8
A9A13 to Y9Y13
FIGURE 5. tSLEW LH Test Load and Waveforms
A1A8 to B1B8
A9A13 to Y9Y13
7 www.fairchildsemi.com

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74LVX161284MTD

Low Voltage IEEE 161284 Translating Transceiver

Fairchild Semiconductor
Fairchild Semiconductor

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