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PDF 74LVX163MTC Data sheet ( Hoja de datos )
| Número de pieza | 74LVX163MTC | |
| Descripción | Low Voltage Synchronous Binary Counter with Synchronous Clear | |
| Fabricantes | Fairchild Semiconductor | |
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October 1996
Revised March 1999
74LVX163
Low Voltage Synchronous Binary Counter with
Synchronous Clear
General Description
The LVX163 is a synchronous modulo-16 binary counter.
This device is synchronously presettable for application in
programmable dividers and has two types of Count Enable
inputs plus a Terminal Count output for versatility in forming
multistage counters. The CLK input is active on the rising
edge. Both PE and MR inputs are active on low logic lev-
els. Presetting is synchronous to rising edge of the CLK
and the Clear function of the LVX163 is synchronous to the
CLK. Two enable inputs (CEP and CET) and Carry Output
are provided to enable easy cascading of counters, which
facilitates easy implementation of n-bit counters without
using external gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise and dynamic
threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX163M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LVX163SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX163MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin
Names
CEP
CET
CP
MR
P0–P3
PE
Q0–Q3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Synchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs
Terminal Count Output
© 1999 Fairchild Semiconductor Corporation DS012157.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = 25°C
TA = −40°C to +85°C Units
(V) Min Typ Max Min Max
Conditions
tPLH Propagation Delay
2.7
9.0
14.0
1.0
16.0
ns CL = 15 pF
tPHL Time (CP–Qn)
11.3 17.0 1.0 19.0
CL = 50 pF
3.3 ± 0.3
8.3
12.8
1.0
15.0
ns CL = 15 pF
10.8
16.3
1.0
18.5
CL = 50 pF
tPLH Propagation Delay
tPHL Time (CP–TC, Count)
2.7
9.5
14.3
1.0
16.7
ns CL = 15 pF
12.5
18.5
1.0
20.5
CL = 50 pF
3.3 ± 0.3
8.7
13.6
1.0
16.0
ns CL = 15 pF
11.2 17.1 1.0 19.5
CL = 50 pF
tPLH Propagation Delay
tPHL Time (CP–TC, Load)
2.7
11.4 18.0
1.0
21.0
ns CL = 15 pF
14.0
21.0
1.0
24.0
CL = 50 pF
3.3 ± 0.3
11.0 17.2
1.0
20.0
ns CL = 15 pF
13.5
20.7
1.0
23.5
CL = 50 pF
tPLH Propagation Delay
2.7
8.6
13.5
1.0
15.0
ns CL = 15 pF
tPHL Time (CET–TC)
11.0 16.5 1.0 18.5
CL = 50 pF
3.3 ± 0.3
7.5
12.3
1.0
14.5
ns CL = 15 pF
10.5
15.8
1.0
18.0
CL = 50 pF
fMAX
Maximum Clock
Frequency
2.7 75 115
50 80
65 MHz CL = 15 pF
45 CL = 50 pF
3.3 ± 0.3
80
55
130
85
70 MHz CL = 15 pF
50 CL = 50 pF
CIN Input Capacitance
4 10
10 pF VCC = Open
CPD Power Dissipation Capacitance
23
pF (Note 4)
Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC.
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ∆ICC which is obtained from the following formula:
CQ0–CQ3 and CTC are the capacitances at Q0–Q3 and TC, respectively. FCP is the input frequency of the CP.
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