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74LVX273MTC PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74LVX273MTC
기능 Low Voltage Octal D-Type Flip-Flop
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74LVX273MTC 데이터시트, 핀배열, 회로
June 1993
Revised March 1999
74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX273M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVX273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
© 1999 Fairchild Semiconductor Corporation DS011614.prf
www.fairchildsemi.com




74LVX273MTC pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
VCC TA = +25°C
(V) Min Typ Max
tPLH Propagation
tPHL Delay Time
CP to Qn
2.7
3.3 ± 0.3
9.0 16.9
11.5 20.0
7.1 11.0
9.6 14.5
tPHL Propagation Delay
MR to Qn
2.7
3.3 ± 0.3
9.3 17.8
11.8 21.1
7.3 11.5
9.8 15.0
tS
tH
tREC
Setup Time
Dn to CP
Hold Time
Dn to CP
Removal Time
MR to CP
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
8.0
5.5
1.0
1.0
4.0
2.5
tW Clock Pulse
Width
2.7
3.3 ± 0.3
8.0
5.5
tW MR Pulse
2.7 7.5
Width
3.3 ± 0.3 5.0
fMAX
Maximum
Clock
2.7 55 110
45 60
Frequency
3.3 ± 0.3 95
150
60 90
tOSLH
Output to Output
2.7
1.5
tOSHL
Skew (Note 4)
3.3
1.5
Note 4: Parameter guaranteed by design. tOSLH = |tPLHm tPLHn|, tOSHL = |tPHLm tPHLn|
TA = −40°C to +85°C
Min Max
1.0 20.5
1.0 24.0
1.0 13.0
1.0 16.5
1.0 20.5
1.0 24.0
1.0 13.5
1.0 17.0
9.5
6.5
1.0
1.0
4.0
2.5
9.5
6.5
8.5
6.0
45
40
80
50
1.5
1.5
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
CL (pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
Capacitance
Symbol
Parameter
TA = +25°C
Min Typ Max
TA = −40°C to +85°C
Min Max
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
4 10
6
31
10
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Units
pF
pF
pF
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74LVX273MTC

Low Voltage Octal D-Type Flip-Flop

Fairchild Semiconductor
Fairchild Semiconductor

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