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74LVX3245 데이터시트 PDF




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부품번호 74LVX3245 기능
기능 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
제조업체 Fairchild Semiconductor
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74LVX3245 데이터시트, 핀배열, 회로
June 2014
74LVX3245
8-Bit, Dual-Supply Translating Transceiver with
3-State Outputs
Features
Bidirectional Interface Between 3 V and 5 V Buses
Inputs Compatible with TTL Level
3 V Data Flow at A-Port and 5 V Data Flow at B-
Port
Outputs Source / Sink: 24 mA
Guaranteed Simultaneous Switching Noise Level
and Dynamic Threshold Performance
Implements Proprietary EMI Reduction Circuitry
Functionally Compatible with the 74 Series 245
Description
The 74LVX3245 is a dual-supply, 8-bit translating
transceiver designed to interface between a 3 V bus and
a 5 V bus in a mixed 5 V supply environment. The
Transmit/ Receive (T/R¯ ) input determines the direction
of data flow. Transmit (active-HIGH) enables data from
A-ports to B-ports; receive (active-LOW) enables data
from B-ports to A-ports. The output enable input, when
HIGH, disables both A- and B-ports by placing them in a
high-impedance condition. The A-port interfaces with
the 3 V bus; the B-port interfaces with the 5 V bus.
The 74LVX3245 is suitable for mixed-voltage
applications, such as notebook computers using 3.3 V
CPU and 5V peripheral components.
Related Resources
AN-5001 — Using Fairchild’s LVX Low-Voltage
Dual-Supply CMOS Translating Transceivers
Ordering Information
Part Number
Operating
Temperature Range
Package
74LVX3245WM
74LVX3245WMX
74LVX3245QSC
74LVX3245QSCX
74LVX3245MTC
74LVX3245MTCX
-40 to +85°C
24-Lead Small-Outline Integrated Circuit
(SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Quarter-Size Outline Package
(QSOP), JEDEC MO-137, 0.150" Wide
24-Lead Thin-Shrink Small-Outline
Package (TSSOP), JEDEC MO-153,
4.4 mm Wide
Packing Method
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.0.3
www.fairchildsemi.com




74LVX3245 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCCA, VCCB Supply Voltage
Parameter
VIN DC Input Voltage; (/OE, T/R¯ )
VI/O DC Input / Output Voltage
An
Bn
IIN DC Input Diode Current (/OE and T/R¯ )
IOK DC Output Diode Current
IO DC Output Source or Sink Current
Output Pin
ICC or IGND DC VCC or Ground Current
TSTG Storage Temperature Range
Maximum Current at
ICCA
ICCB
ISINK DC Latch-Up Source or Sink Current
TJ Maximum Junction Temperature Under Bias
ESD
Electrostatic Discharge
Capability
Human Body Model, JESD22-A114
Min.
-0.5
-0.5
-0.5
-0.5
-65
Max.
7.0
VCCA
+0.5
VCCA to
+0.5
VCCB to
+0.5
±20
±50
±50
±50
±100
±200
+150
±300
+150
Unit
V
V
V
mA
mA
mA
mA
°C
mA
°C
2500
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCCA
VCCB
Supply Voltage
VI Input Voltage (/OE and T/R¯ )
VI/O DC Input / Output Voltage
An
Bn
TA Operating Temperature, Free Air
t / V
Minimum Input Edge Rate (VIN from 30 to 70% of VCC, VCC at 3.0 V,
4.5 V, and 5.5 V)
Note:
1. Unused pins (inputs and I/O’s) must be held HIGH or LOW. They may not float.
Min.
2.7
4.5
0
0
0
-40
Max.
3.6
5.5
VCCA
VCCA
VCCB
+85
8
Unit
V
V
V
°C
ns/V
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.0.3
4
www.fairchildsemi.com

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74LVX3245 전자부품, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
TA=+25°C, CL=50 pF,
VCCA=3.3 V(5),
VCCB=5.0 V(6)
TA=-40 to +85°C,
CL=50 pF,
VCCA=3.3 V(5),
VCCB=5.0 V(6)
TA=-40 to +85°C,
CL=50 pF,
VCCA=2.7 V,
VCCB=5.0 V
Units
Min. Typ. Max.
Min.
Max.
Min.
Max.
tPHL, tPLH
Propagation
Delay A to B
Propagation
Delay B to A
1.0 5.4
1.0 5.6
1.0 5.1
1.0 5.7
8.0
7.5
7.5
7.5
1.0
1.0
1.0
1.0
8.5 1.0 9.0
8.0 1.0 8.5
ns
8.0 1.0 8.5
8.0 1.0 8.5
tPZL, tPZH
Output Enable
Time /OE to B
Output Enable
Time /OE to A
1.0 4.8
1.0 6.3
1.0 6.3
1.0 6.8
8.0
8.5
8.5
9.0
1.0
1.0
1.0
1.0
8.5 1.0 9.0
9.0 1.0 9.5
ns
9.0 1.0 9.5
9.5 1.0 10.0
Output Disable 1.0 5.3
Time /OE to B
1.0 4.2
tPHZ, tPLZ
Output Disable 1.0 5.3
Time /OE to A
1.0 3.7
7.5
7.0
8.0
6.5
1.0
1.0
1.0
1.0
8.0 1.0 8.5
7.5 1.0 8.0
ns
8.5 1.0 9.0
7.0 1.0 7.5
Output to Output
tOSHL, tOSLH Skew, Data to
Output(7)
1.0 1.5
1.5 1.5 ns
Notes:
5. Voltage range 3.3 V is 3.3 V ± 0.3 V.
6. Voltage range 5.0 V is 5.0 V ± 0.5 V.
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
CIN Input Capacitance
CI/O Input / Output Capacitance
CPD Power Dissipation Capacitance(8)
Note:
8. CPD is measured at 10 MHz.
A to B
B to A
Conditions
VCC = Open
VCCA = 3.3 V,
VCCB = 5.0 V
VCCA = 3.3 V,
VCCB = 5.0 V
Typ.
4.5
15
55
40
Units
pF
pF
pF
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.0.3
7
www.fairchildsemi.com

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