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부품번호 74LVX3245QSC 기능
기능 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
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74LVX3245QSC 데이터시트, 핀배열, 회로
July 1993
Revised July 1999
74LVX3245
8-Bit Dual Supply Translating Transceiver with
3-STATE Outputs
General Description
The LVX3245 is a dual-supply, 8-bit translating transceiver
that is designed to interface between a 3V bus and a 5V
bus in a mixed 3V/5V supply environment. The Transmit/
Receive (T/R) input determines the direction of data flow.
Transmit (active-HIGH) enables data from A Ports to B
Ports; Receive (active-LOW) enables data from B Ports to
A Ports. The Output Enable input, when HIGH, disables
both A and B Ports by placing them in a high impedance
condition. The A Port interfaces with the 3V bus; the B Port
interfaces with the 5V bus.
The LVX3245 is suitable for mixed voltage applications
such as notebook computers using 3.3V CPU and 5V
peripheral components.
Features
s Bidirectional interface between 3V and 5V buses
s Inputs compatible with TTL level
s 3V data flow at A Port and 5V data flow at B Port
s Outputs source/sink 24 mA
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Implements proprietary EMI reduction circuitry
s Functionally compatible with the 74 series 245
Ordering Code:
Order Number Package Number
Package Description
74LVX3245WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVX3245QSC
MQA24
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
74LVX3245MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
T/R
A0–A7
B0–B7
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011620
www.fairchildsemi.com




74LVX3245QSC pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (Continued)
Symbol
Parameter
VCCA
(V)
VCCB
(V)
TA = +25°C
TA = −40°C to +85°C Units
Typ Guaranteed Limits
Conditions
ICC
Maximum
Bn 3.6 5.5 1.0 1.35 1.5 mA VI = VCCB 2.1V
ICCT/Input @
An, T/R,
OE
3.6 5.5
0.35
0.5 mA VI = VCCA 0.6V
ICCA
Quiescent VCCA
Supply Current
3.6 5.5
An = VCCA or GND
5 50 µA Bn = VCCB or GND,
OE = GND, T/R = GND
ICCB
Quiescent VCCB
Supply Current
3.6 5.5
An = VCCA or GND
8 80 µA Bn = VCCB or GND,
VOLPA Quiet Output Maximum
VOLPB Dynamic VOL
VOLVA Quiet Output Minimum
VOLVB
Dynamic VOL
VIHDA
Minimum HIGH Level
VIHDB
Dynamic Input Voltage
VILDA
Maximum LOW Level
VILDB
Dynamic Input Voltage
Note 3: Worst case package.
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
3.3 5.0
0.8
1.5
0.8
1.2
2.0
2.0
0.8
0.8
OE = GND, T/R = VCCA
V (Note 3) (Note 4)
V (Note 3) (Note 4)
V (Note 3) (Note 5)
V (Note 3) (Note 5)
Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND.
Note 5: Max number of Data Inputs (n) switching. (n1) inputs switching 0V to VCC level. Input-under-test switching:
VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz.
AC Electrical Characteristics
TA = +25°C
TA = −40°C to +85°C TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
CL = 50 pF
Symbol
Parameters
VCCA = 3.3V (Note 6)
VCCA = 3.3V (Note 6)
VCCA = 2.7V
Units
VCCB = 5.0V (Note 7)
VCCB = 5.0V (Note 7) VCCB = 5.0V (Note 7)
Min Typ Max Min Max Min Max
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
Propagation Delay
A to B
Propagation Delay
B to A
Output Enable
Time OE to B
1.0 5.4 8.0 1.0 8.5 1.0 9.0
ns
1.0 5.6 7.5 1.0 8.0 1.0 8.5
1.0 5.1 7.5 1.0 8.0 1.0 8.5
ns
1.0 5.7 7.5 1.0 8.0 1.0 8.5
1.0 4.8 8.0 1.0 8.5 1.0 9.0
ns
1.0 6.3 8.5 1.0 9.0 1.0 9.5
tPZL
tPZH
Output Enable
Time OE to A
1.0 6.3 8.5 1.0 9.0 1.0 9.5
ns
1.0 6.8 9.0 1.0 9.5 1.0 10.0
tPHZ Output Disable
tPLZ Time OE to B
1.0 5.3 7.5 1.0 8.0 1.0 8.5
ns
1.0 4.2 7.0 1.0 7.5 1.0 8.0
tPHZ Output Disable
tPLZ Time OE to A
1.0 5.3 8.0 1.0 8.5 1.0 9.0
ns
1.0 3.7 6.5 1.0 7.0 1.0 7.5
tOSHL
tOSLH
Output to Output
Skew (Note 8)
Data to Output
1.0 1.5 1.5 1.5 ns
Note 6: Voltage Range 3.3V is 3.3V ± 0.3V.
Note 7: Voltage Range 5.0V is 5.0V ± 0.5V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
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74LVX3245QSC 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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74LVX3245QSC

8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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