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74LVX374MTC PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74LVX374MTC
기능 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
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74LVX374MTC 데이터시트, 핀배열, 회로
October 1993
Revised March 1999
74LVX374
Low Voltage Octal D-Type Flip-Flop with
3-STATE Outputs
General Description
The LVX374 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-
flops. The inputs tolerate up to 7V allowing interface of 5V
systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX374M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LVX374SJ
74LVX374MTC
M20D
MTC20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011612.prf
www.fairchildsemi.com




74LVX374MTC pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
VCC TA = +25°C
(V)
Min Typ Max
fMAX
Maximum Clock
Frequency
2.7 60 115
45 60
3.3 ± 0.3 100
160
60 95
tPLH Propagation Delay Time
tPHL CP to On
2.7
3.3 ± 0.3
8.5 16.3
11.0 19.8
6.7 10.6
9.2 14.1
tPZL 3-STATE Output
tPZH
Enable Time
2.7
3.3 ± 0.3
7.6
10.1
5.9
14.5
18.0
9.3
8.4 12.8
tPLZ 3-STATE Output
tPHZ Disable Time
tW CP Pulse
Width
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
7.5
5.0
11.5 18.5
9.6 13.2
tS Setup Time
2.7 6.5
Dn to CP
3.3 ± 0.3 4.5
tH Hold Time
2.7 2.0
Dn to CP
3.3 ± 0.3 2.0
tOSLH
Output to Output
2.7
1.5
tOSHL
Skew (Note 4)
3.3
1.5
Note 4: Parameter guaranteed by design. tOSLH = |tPLHm tPLHn|, tOSHL = |tPHLm tPHLn|
TA = −40°C to
+85°C
Min Max
50
40
85
55
1.0 19.5
1.0 23.0
1.0 12.5
1.0 16.0
1.0 17.5
1.0 21.0
1.0 11.0
1.0 14.5
1.0 22.0
1.0 15.0
8.0
5.5
6.5
4.5
2.0
2.0
1.5
1.5
Units
Conditions
MHz
ns
ns
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF, RL = 1 k
CL = 50 pF, RL = 1 k
CL = 15 pF, RL = 1 k
CL = 50 pF, RL = 1 k
CL = 50 pF, RL = 1 k
CL = 50 pF, RL = 1 k
ns
ns
ns
ns CL = 50 pF
Capacitance
Symbol
Parameter
TA = +25°C
Min Typ Max
TA = −40°C to +85°C
Min Max
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
4 10
6
32
10
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Units
pF
pF
pF
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74LVX374MTC

Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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