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부품번호 | 74LVX573MTC 기능 |
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기능 | Low Voltage Octal Latch with 3-STATE Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
June 1993
Revised March 1999
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVX573 is functionally identical to
the LVX373 but with inputs and outputs on opposite sides
of the package. The inputs tolerate up to 7V allowing inter-
face of 5V systems to 3V systems.
Features
s Input voltage translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number Package Number
Package Description
74LVX573M
74LVX573SJ
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
© 1999 Fairchild Semiconductor Corporation DS011616.prf
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
VCC TA = +25°C
(V) Min Typ Max
tPLH
tPHL
Propagation
Delay Time
Dn to On
2.7
3.3 ± 0.3
7.6
10.1
5.9
8.4
14.5
18.0
9.3
12.8
tPLH
tPHL
Propagation
Delay Time
LE to On
2.7
3.3 ± 0.3
8.2
10.7
6.4
8.9
15.6
19.1
10.1
13.6
tPZL 3-STATE Output
tPZH
Enable Time
2.7
3.3 ± 0.3
7.8
10.3
6.1
15.0
18.5
9.7
8.6 13.2
tPLZ
tPHZ
tW
3-STATE Output
Disable Time
LE Pulse
Width
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
6.5
5.0
12.1
10.1
19.1
13.6
tS Setup Time
2.7 5.0
Dn to LE
3.3 ± 0.3 3.5
tH Hold Time
2.7 1.5
Dn to LE
3.3 ± 0.3 1.5
tOSHL
Output to Output
2.7
1.5
tOSLH
Skew (Note 4)
2.3
1.5
Note 4: Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
TA = −40°C to +85°C
Min Max
1.0 17.5
1.0 21.0
1.0 11.0
1.0 14.5
1.0 18.5
1.0 22.0
1.0 12.0
1.0 15.5
1.0 18.5
1.0 22.0
1.0 12.0
1.0 15.5
1.0 22.0
1.0 15.5
7.5
5.0
5.0
3.5
1.5
1.5
1.5
1.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF, RL = 1 kΩ
CL = 50 pF, RL = 1 kΩ
CL = 15 pF, RL = 1 kΩ
CL = 50 pF, RL = 1 kΩ
CL = 50 pF, RL = 1 kΩ
CL = 50 pF, RL = 1 kΩ
CL = 50 pF
Capacitance
Symbol
Parameter
TA = +25°C
Min Typ Max
TA = −40°C to +85°C
Min Max
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance (Note 5)
4 10
6
27
10
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Units
pF
pF
pF
www.fairchildsemi.com
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74LVX573MTC | Low Voltage Octal Latch with 3-STATE Outputs | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |