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부품번호 | 74LVX74SJ 기능 |
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기능 | Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 6 페이지수
May 1993
Revised March 1999
74LVX74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
General Description
The LVX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
s Input voltage level translation from 5V to 3V
s Ideal for low power/low noise 3.3V applications
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX74M
74LVX74SJ
Package Number
Package Description
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS011606.prf
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
VCC TA = +25°C
(V) Min Typ
tPLH
tPHL
Propagation Delay
CPn to Qn or Qn
2.7
3.3 ± 0.3
7.3
9.8
5.7
8.2
tPLH
tPHL
Propagation Delay
CDn to SDn to Qn or Qn
2.7
3.3 ± 0.3
8.4
10.9
6.6
9.1
tW CPn or CDn or SDn
Pulse Width
2.7
3.3 ± 0.3
8.5
6
tS
tH
tREC
fMAX
Setup Time
Dn to CPn
Hold Time
Dn to CPn
Recovery Time
CPn or SDn to CPn
Maximum Clock Frequency
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
3.3 ± 0.3
2.7
8.0
5.5
0.5
0.5
6.5
5.0
55
45
135
60
3.3 ± 0.3 95
145
60 85
tOSLH
Output to Output Skew
2.7
tOSHL
(Note 4)
3.3
Note 4: Parameter guaranteed by design. tOSLH = |tPLHm–tPLHn|, tOSLH = |tPHLm–tPHLn|
Max
15
18.5
9.7
13.2
15.6
19.1
10.1
13.6
1.5
1.5
TA = −40°C to +85°C
Min Max
1.0 18.5
1.0 22
1.0 11.5
1.0 15
1.0 18.5
1.0 22
1.0 12
1.0 15.5
10
7
9.5
6.5
0.5
0.5
7.5
5.0
50
40
80
50
1.5
1.5
Units
ns
ns
ns
ns
ns
ns
MHz
ns
CL (pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
Capacitance
Symbol
Parameter
TA = +25°C
Min Typ Max
TA = −40°C to +85°C
Min Max
CIN Input Capacitance
CPD Power Dissipation
Capacitance (Note 5)
4 10
25
10
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Units
pF
pF
www.fairchildsemi.com
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74LVX74SJ | Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop | Fairchild Semiconductor |
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