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부품번호 | 74VCX162601 기능 |
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기능 | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 8 페이지수
April 1998
Revised April 1999
74VCX162601
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V
Tolerant Inputs and Outputs and 26Ω Series Resistors in
the B-Port Outputs
General Description
The VCX162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the HIGH-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCX162601 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCX162601 is also designed with 26Ω series resistors
in the B-Port outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in B-Port outputs
s tPD (A to B)
3.8 ns max for 3.0V to 3.6V VCC
4.6 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL B outputs)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX162601MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CLKAB, CLKBA
CLKENAB, CLKENBA
A1–A18
B1–B18
Description
Output Enable Inputs (Active LOW)
Latch Enable Inputs
Clock Inputs
Clock Enable Inputs
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS500150.prf
www.fairchildsemi.com
DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
B Outputs
HIGH Level Output Voltage
A Outputs
VOL LOW Level Output Voltage
B Outputs
LOW Level Output Voltage
A Outputs
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF
Power Off Leakage Current
ICC Quiescent Supply Current
Note 9: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −4 mA
IOH = −6 mA
IOH = −8 mA
IOH = − 100µA
IOH = −6 mA
IOH = −12 mA
IOH = −18 mA
IOL = 100 µA
IOL = 6 mA
IOL = 8 mA
IOL = 100 µA
IOL = 12 mA
IOL = 18 mA
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
VCC ≤ (VI, VO) ≤ 3.6V (Note 9)
VCC
(V)
2.3 − 2.7
2.3 − 2.7
2.3 − 2.7
2.3
2.3
2.3
2.3 − 2.7
2.3
2.3
2.3
2.3 − 2.7
2.3
2.3
2.3 − 2.7
2.3
2.3
2.3 − 2.7
2.3 − 2.7
Min
1.6
VCC − 0.2
2.0
1.8
1.7
VCC − 0.2
2.0
1.8
1.7
Max
0.7
0.2
0.4
0.6
0.2
0.4
0.6
±5.0
±10
0
2.3 − 2.7
2.3 − 2.7
10
20
±20
DC Electrical Characteristics (1.65V ≤ VCC < 2.3V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
B Outputs
HIGH Level Output Voltage
A Outputs
VOL LOW Level Output Voltage
B Outputs
LOW Level Output Voltage
A Outputs
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF
Power Off Leakage Current
ICC Quiescent Supply Current
Note 10: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −3 mA
OH = −100 µA
IOH = −6 mA
IOL = 100 µA
IOL = 3 mA
IOL = 100 µA
IOL = 6 mA
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
VCC ≤ (VI, VO) ≤ 3.6V (Note 10)
VCC
(V)
1.65 - 2.3
1.65 - 2.3
1.65 - 2.3
1.65
1.65 - 2.3
1.65
1.65 - 2.3
1.65
1.65 - 2.3
1.65
1.65 - 2.3
1.65 - 2.3
Min Max
0.65 × VCC
VCC − 0.2
1.4
0.35 × VCC
VCC − 0.2
1.25
0.2
0.3
0.2
0.3
±5.0
±10
0
1.65 - 2.3
1.65 - 2.3
10
20
±20
Units
V
V
V
V
V
V
µA
µA
µA
µA
Units
V
V
V
V
V
V
µA
µA
µA
µA
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4
4페이지 AC Loading and Waveforms
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
FIGURE 1. AC Test Circuit
SWITCH
Open
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V
GND
FIGURE 2. Waveform for Inverting and
Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
trec Waveforms
Symbol
Vmi
Vmo
VX
VY
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 8 페이지수 | ||
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74VCX162601 | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs | Fairchild Semiconductor |
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