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PDF 74VCX162835 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX162835 | |
| Descripción | Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26 Series Resistors in Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1998
Revised April 2000
74VCX162835
Low Voltage 18-Bit Universal Bus Driver with
3.6V Tolerant Inputs/Outputs
and 26Ω Series Resistors in Outputs
General Description
Features
The VCX162835 low voltage 18-bit universal bus driver s Compatible with PC100 DIMM module specifications
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
s 1.65V–3.6V VCC specifications provided
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in outputs
s tPD (CP to On)
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (In) to Outputs (On) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The VCX162835 is designed with 26Ω series resistors in
the outputs. This design reduces noise in applications such
4.2ns max for 3.0V to 3.6V VCC
5.2ns max for 2.3V to 2.7V VCC
9.2ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL)
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
±12mA @ 3.0V VCC
±8 mA @ 2.3V VCC
The 74VCX162835 is designed for low voltage (1.65V to
±3 mA @ 1.65V VCC
3.6V) VCC applications with I/O capability up to 3.6V. www.DataSsheLeta4Utc.choump performance exceeds 300 mA
The 74VCX162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high impedance state during power up or power
down, OE should be tied to VCC through a pulldown resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX162835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS500181
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 10)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5 ± 0.2V
VCC = 1.8 ± 0.15V
Units
Min Max Min Max Min Max
fMAX
tPHL, tPLH
Maximum Clock Frequency
Propagation Delay
Bus to Bus
250 200 100
0.6 3.9 0.8 5.0 1.5 9.8
MHz
ns
tPHL, tPLH
Propagation Delay
Clock to Bus
1.4 4.2 1.5 5.2 2.0 9.2
ns
tPHL, tPLH
Propagation Delay
LE to Bus
0.6 4.7 0.8 5.8 1.5 9.8
ns
tPZL, tPZH
Output Enable Time
0.6 4.3 0.8 5.9 1.5 9.8
tPLZ, tPHZ
Output Disable Time
0.6 4.2 0.8 4.7 1.5 7.9
tS Setup Time
1.5 1.5 2.5
tH Hold Time
0.7 0.7 1.0
tW Pulse Width
1.5 1.5 4.0
tOSHL
tOSLH
Output to Output Skew
(Note 11)
0.5 0.5 0.75
Note 10: For CL=50pF, add approximately 300ps to the AC maximum specification.
ns
ns
ns
ns
ns
ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
AC Electrical Characteristics Over Load (Note 12)
TA = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.15V
Symbol
Parameter
CL = 0 pF
CL = 50 pF
Min Max Min Max
tPHL, tPLH
Prop Delay Bus to Bus
0.7 2.6 1.0 4.2
tPHL, tPLH
Prop Delay Clock to Bus
1.4 2.9 1.9 4.5
tPHL, tPLH
Prop Delay LE to Bus
0.7 3.4 1.0 5.0
tPZL, tPZH
Output Enable Time
0.7 3.0 1.0 4.6
tPLZ, tPHZ
Output Disable Time
0.7 2.9 1.0 4.5
tPHL, tPLH
SSO Prop Delay Clock to Bus (Note 13)
1.4
3.2
tS Setup Time
1.5 1.5
tH Hold Time
0.7 0.7
Note 12: Characterized only.
Note 13: SSO=Simultaneous Switching Output. Any output combination of LOW-to-HIGH and/or HIGH-to-LOW transition.
Units
ns
ns
ns
ns
ns
ns
ns
ns
Dynamic Switching Characteristics
Symbol
VOLP
Parameter
Conditions
Quiet Output Dynamic Peak VOL CL = 30 pF, VIH = VCC, VIL = 0V
VOLV
Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V
VOHV
Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V
VCC
TA=+25°C
Units
(V) Typical
1.8 0.25
2.5 0.35 V
3.3 0.45
1.8 −0.25
2.5 −0.35 V
3.3 −0.45
1.8 1.35
2.5 1.85 V
3.3 2.45
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74VCX162835.PDF ] | |
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