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PDF 74VCX164245 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX164245 | |
| Descripción | Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 2000
Revised March 2000
74VCX164245
Low Voltage 16-Bit Dual Supply Translating Transceiver
with 3-STATE Outputs
General Description
Features
The VCX164245 is a dual supply, 16-bit translating trans- s Bidirectional interface between busses ranging from
ceiver that is designed for 2 way asynchronous communi-
1.65V to 3.6V
cation between busses at different supply voltages by
providing true signal translation. The supply rails consist of
VCCB, which is the higher potential rail operating at 2.3 to
3.6V and VCCA, which is the lower potential rail operating at
s Supports Live Insertion and Withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
1.65 to 2.7V. (VCCA must be less than or equal to VCCB for
±18 mA @ 2.3V VCC
proper device operation.) This dual supply design allows
for translation from 1.8V to 2.5V busses to busses at a
higher potential, up to 3.3V.
The Transmit/Receive (T/R) input determines the direction
of data flow. Transmit (active-HIGH) enables data from A
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Functionally compatible with 74 series 16245
s Latchup performance exceeds 300 mA
Ports to B Ports; Receive (active-LOW) enables data from s ESD performance:
B Ports to A Ports.The Output Enable (OE) input, when
HIGH, disables both A and P Ports by placing them in a
High-Z condition. The A Port interfaces with the lower volt-
Human Body Model >2000V
Machine model >200V
age bus (1.8 − 2.5V); The B Port interfaces with the higher
voltage bus (2.7 − 3.3V). Also the VCX164245 is designed
so that the control pins (T/Rn, OEn) are supplied by VCCBw.ww.DataSNhoeteet41U:.cToomensure the high impedance state during power up or power
The 74VCX164245 is suitable for mixed voltage applica-
tions such as notebook computers using a 1.8V CPU and
3.3V peripheral components. It is fabricated with an
down, OEn should be tied to VCCB through a pull up resistor. The minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Advanced CMOS technology to achieve high speed opera-
tion while maintaining low CMOS power dissipation.
Ordering Code:
Order Number Package Number
Package Description
74VCX164245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Diagram
Pin Descriptions
Pin Names
OEn
T/Rn
A0–A15
B0–B15
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS500159
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
CL = 30 pF, RL = 500Ω, TA = −40°C to +85°C,
Symbol
Parameter
VCCA = 1.65V to 1.95V
VCCB = 2.3V to 2.7V
VCCA = 1.65V to 1.95V
VCCB = 3.0V to 3.6V
VCCA = 2.3V to 2.7V
VCCB = 3.0V to 3.6V
Units
Min Max Min Max Min Max
tPHL, tPLH Prop Delay, A to B
0.8 5.5 0.6 5.1 0.6 4.0 ns
tPHL, tPLH Prop Delay, B to A
1.5 5.8 1.5 6.2 0.8 4.4 ns
tPZL, tPZH Output Enable Time, OE to B
0.8 5.3 0.6 5.1 0.6 4.0 ns
tPZL, tPZH Output Enable Time, OE to A
1.5 8.3 1.5 8.2 0.8 4.6 ns
tPLZ, tPHZ Output Disable Time, OE to B
0.8 5.2 0.8 5.6 0.8 4.8 ns
tPLZ, tPHZ Output Disable Time, OE to A
0.8 4.6 0.8 4.5 0.8 4.4 ns
tosHL
tosLH
Output to Output Skew
(Note 6)
0.5
0.5
0.75
ns
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tosHL) or LOW-to-HIGH (tosLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL,
B to A
Quiet Output Dynamic Peak VOL,
A to B
VOLV
Quiet Output Dynamic Valley VOL,
B to A
Quiet Output Dynamic Valley VOL,
A to B
VOHV
Quiet Output Dynamic Valley VOH,
A to B
Quiet Output Dynamic Valley VOH,
B to A
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
VCCA
(V)
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
1.8
1.8
2.5
VCCB
(V)
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
2.5
3.3
3.3
TA = 25°C
Typical
0.25
0.25
0.6
0.6
0.8
0.8
−0.25
−0.25
−0.6
−0.6
−0.8
−0.8
1.7
2.0
2.0
1.3
1.3
1.7
Units
V
V
V
V
V
V
Capacitance
Symbol
Parameter
CIN Input Capacitance
CI/O Input/Output Capacitance
CPD Power Dissipation Capacitance
Conditions
VCCA = 2.5V, VCCB = 3.3V, VI = 0V or VCCA/B
VCCA = 2.5V, VCCB = 3.3V, VI = 0V or VCCA/B
VCCA = 2.5V, VCCB = 3.3V, VI = 0V or VCCA/B
f = 10 MHz
TA = +25°C
Typical
5
6
20
Units
pF
pF
pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VCX164245.PDF ] | |
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