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PDF 74VCX16721 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX16721 | |
| Descripción | Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1998
Revised April 1999
74VCX16721
Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant
Inputs and Outputs
General Description
Features
The VCX16721 contains twenty non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications.
The 74VCX16721 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX16721 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
s 1.8V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (CLK to On)
3.5 ns max for 3.0V to 3.6V VCC
4.4 ns max for 2.3V to 2.7V VCC
8.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
www.DataSheet4U.com
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16721MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
CLK
D0–D19
O0–O19
CE
Description
Output Enable Input (Active LOW)
Clock Input
Inputs
Outputs
Clock Enable Input (Active LOW)
© 1999 Fairchild Semiconductor Corporation DS500143.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 8)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5V ± 0.2V
VCC = 1.8V ± 0.15V
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
250
200
100 MHz
tPHL, tPLH Prop Delay CLK to On
0.8 3.5 1.0 4.4 1.5 8.8 ns
tPZL, tPZH Output Enable Time
0.8 3.8 1.0 4.9 1.5 9.8 ns
tPLZ, tPHZ Output Disable Time
0.8 3.7 1.0 4.2 1.5 7.6 ns
tS Setup Time
1.5 1.5 2.5
ns
tH Hold Time
1.0 1.0 1.0
ns
tW Pulse Width
1.5 1.5 4.0 ns
tOSHL
tOSLH
Output to Output Skew
(Note 9)
0.5 0.5 0.75 ns
Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
VOHV
Quiet Output Dynamic Valley VOH
Conditions
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
CL = 30 pF, VIH = VCC, VIL = 0V
V CC
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
TA = +25°C
Typical
0.25
0.6
0.8
−0.25
−0.6
−0.8
1.5
1.9
2.2
Units
V
V
V
Capacitance
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz,
VCC = 1.8V, 2.5V or 3.3V
TA = +25°C
Typical
6
7
20
Units
pF
pF
pF
5 www.fairchildsemi.com
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| PDF Descargar | [ Datasheet 74VCX16721.PDF ] | |
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