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PDF 74VCX16722 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX16722 | |
| Descripción | Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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February 1999
Revised January 2005
74VCX16722
Low Voltage 22-Bit Register
with 3.6V Tolerant Inputs and Outputs
General Description
Features
The VCX16722 low voltage 22-bit register contains twenty-
two non-inverting D-type flip-flops with 3-STATE outputs
and is intended for bus oriented applications. The design
has been optimized for use with JEDEC compliant 200 pin
DIMM modules.
The 74VCX16722 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16722 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (CLK to On)
3.6ns max for 3.0V to 3.6V VCC
4.6ns max for 2.3V to 2.7V VCC
9.2ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Meets JEDEC registered module specifications
s Static Drive (IOH/IOL)
±24mA @ 3.0V
±18mA @ 2.3V
±6mA @ 1.65V
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
www.DataSheet4MU.caocmhine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16722MTD
MTD64
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation DS500192
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 8)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5 ± 0.2V
VCC = 1.8 ± 0.15V
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
250
200
100
MHz
tPHL, tPLH
Propagation Delay Clock to Bus
1.3
3.6
1.5
4.6
2.0
9.2
ns
tPZL, tPZH
Output Enable Time
0.6 3.5 0.8 4.5 1.5 9.0
ns
tPLZ, tPHZ
Output Disable Time
0.6 3.2 0.8 4.2 1.5 7.6
ns
tS Setup Time
2.0 2.0 3.0
ns
tH Hold Time
0.0 0.0 0.5
ns
tW Pulse Width
1.5 1.5 4.0
ns
tOSHL
tOSLH
Output to Output Skew
(Note 9)
0.5
0.5
0.75
ns
Note 8: For CL= 50 pF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
AC Electrical Characteristics Over Load (Note 10)
TA = −0°C to +70°C, RL = 500Ω VCC = 3.3V ± 0.3V
Symbol
Parameter
CL = 0 pF
CL = 50 pF
Min Max Min Max
tPHL, tPLH
Propagation Delay Clock to Bus
1.1 2.5 1.9 3.9
tPZL, tPZH
Output Enable Time
0.7 2.4 1.0 3.8
tPLZ, tPHZ
Output Disable Time
0.7 2.1 1.0 3.5
tS Setup Time
2.0 2.0
tH Hold Time
0.0 0.0
tW Pulse Width
1.5 1.5
Note 10: This parameter is guaranteed by characterization but not tested.
Units
ns
ns
ns
ns
ns
ns
Dynamic Switching Characteristics
Symbol
VOLP
Parameter
Conditions
Quiet Output Dynamic Peak VOL CL = 30 pF, VIH = VCC, VIL = 0V
VOLV
Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V
VOHV
Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V
VCC
TA = +25°C
Units
(V) Typical
1.8 0.25
2.5 0.6 V
3.3 0.8
1.8 −0.25
2.5 −0.6 V
3.3 −0.8
1.8 1.5
2.5 1.9 V
3.3 2.2
5 www.fairchildsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74VCX16722.PDF ] | |
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