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74VCX16835 데이터시트 PDF




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부품번호 74VCX16835 기능
기능 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs
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74VCX16835 데이터시트, 핀배열, 회로
www.DataSheet4U.com
October 1998
Revised April 2000
74VCX16835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (In) to Ouputs (On) on a
Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74VCX16835 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 DIMM module specifications
s 1.65V–3.6V VCC specifications provided
s 3.6V tolerant inputs and outputs
s tPD (CP to On)
4.2ns max for 3.0V to 3.6V VCC
5.2ns max for 2.3V to 2.7V VCC
9.2ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24mA @ 3.0V
±18mA @ 2.3V
±6mA @ 1.65V
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC (OE to GND) through a pulldown resistor;
the minimum value of the resistor is determined by the current sourcing
capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2000 Fairchild Semiconductor Corporation DS500173
www.fairchildsemi.com




74VCX16835 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics (2.3V VCC 2.7V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power Off Leakage Current
ICC Quiescent Supply Current
Note 8: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −6 mA
IOH = −12 mA
IOH = −18 mA
IOL = 100 µA
IOL = 12mA
IOL = 18 mA
0 VI 3.6V
0 VO 3.6V
VI = VIH or VIL
0 (VI, VO) 3.6V
VI = VCC or GND
VCC (VI, VO) 3.6V (Note 8)
VCC
(V)
2.3 - 2.7
2.3 - 2.7
2.3 -2.7
2.3
2.3
2.3
2.3 - 2.7
2.3
2.3
2.3 - 2.7
2.3 - 2.7
0
2.3 - 2.7
2.3 - 2.7
Min
1.6
VCC 0.2
2.0
1.8
1.7
Max
0.7
0.2
0.4
0.6
±5.0
±10
10
20
±20
DC Electrical Characteristics (1.65V VCC < 2.3V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power Off Leakage Current
ICC Quiescent Supply Current
Note 9: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −6 mA
IOL = 100 µA
IOL = 6mA
0 VI 3.6V
0 VO 3.6V
VI = VIH or VIL
0 (VI, VO) 3.6V
VI = VCC or GND
VCC (VI, VO) 3.6V (Note 9)
VCC
(V)
1.65 - 2.3
1.65 - 2.3
1.65 - 2.3
1.65
1.65 - 2.3
1.65
1.65 - 2.3
1.65 - 2.3
Min Max
0.65 × VCC
VCC 0.2
1.25
0.35 × VCC
0.2
0.3
±5.0
±10
0
1.65 - 2.3
1.65 - 2.3
10
20
±20
Units
V
V
V
V
µA
µA
µA
µA
Units
V
V
V
V
µA
µA
µA
µA
www.fairchildsemi.com
4

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74VCX16835 전자부품, 판매, 대치품
AC Loading and Waveforms
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
FIGURE 3. AC Test Circuit
SWITCH
Open
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V to ± 0.15V
GND
FIGURE 4. Waveform for Inverting and
Non-inverting Functions
tr = tf 2.0ns, 10% to 90%
FIGURE 5. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
tr = tf 2.0ns, 10% to 90%
FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
tr = tf 2.0ns, 10% to 90%
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
1.8 ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
7 www.fairchildsemi.com

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