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K8D1716U 데이터시트 PDF




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부품번호 K8D1716U 기능
기능 16M Dual Bank NOR Flash Memory
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K8D1716U 데이터시트, 핀배열, 회로
K8D1716UTB / K8D1716UBB
FLASH MEMORY
Document Title
16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory
Revision History
Revision No. History
0.0 Initial Draft
Draft Date
July 25, 2004
Remark
Advance
1 Revision 0.0
July 2004




K8D1716U pdf, 반도체, 판매, 대치품
K8D1716UTB / K8D1716UBB
FLASH MEMORY
ORDERING INFORMATION
K 8 D 17 1 6 U T B - T I 0 7
Samsung
NOR Flash Memory
Device Type
Dual Bank Boot Block
Access Time
07 = 70 ns
08 = 80 ns
09 = 90 ns
Operating Temperature Range
C = Commercial Temp. (0 °C to 70 °C)
I = Industrial Temp. (-40 °C to 85 °C)
Bank Division
17 = 8Mbits + 8Mbits
Organization
x16
Package
Y = 48 TSOP1
Version
B = 3rd Generation
Operating Voltage Range
2.7V to 3.6V
Block Architecture
T = Top Boot Block
B = Bottom Boot Block
Table 1. PRODUCT LINE-UP
Part No.
Vcc
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
-7
70ns
70ns
25ns
-8
2.7V~3.6V
80ns
80ns
25ns
-9
90ns
90ns
35ns
Table 2. K8D1716U DEVICE BANK DIVISIONS
Device
Part Number
K8D1716U
Mbit
8 Mbit
Bank 1
Block Sizes
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Mbit
8 Mbit
Bank 2
Block Sizes
Sixteen
64 Kbyte/32 Kword
4 Revision 0.0
July 2004

4페이지










K8D1716U 전자부품, 판매, 대치품
K8D1716UTB / K8D1716UBB
FLASH MEMORY
PRODUCT INTRODUCTION
The K8D1716U is a 16Mbit (16,777,216 bits) NOR-type Flash memory. The device features single voltage power supply operating
within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is
used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flex-
ible erase and program capability, the device adapts a block memory architecture that divides its memory array into 39 blocks (64-
Kbyte x 31 , 8-Kbyte x 8). Programming is done in units of 8 bits (Byte) or 16 bits (Word). All bits of data in one or multiple blocks can
be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writ-
ing the programmed data, 39 memory blocks can be hardware protected by the block group. Byte/Word modes are available for read
operation. These modes can be selected via BYTE pin. The device provides read access times of 70ns, 80ns and 90ns supporting
high speed microprocessors to operate without any wait states.
The command set of K8D1716U is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output
enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be com-
bined wih addresses and data are sequentially written to the command registers using microprocessor write timing. The command
codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch
addresses and data necessary to execute the program and erase operations. The K8D1716U is implemented with Internal Program/
Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase
command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal
Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The
K8D1716U has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY
pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to
the read mode. The device requires only 14 mA as active read current and 15 mA for program/erase operations.
Table 7. Operations Table
Operation
CE OE WE BYTE
Read
word L L H
byte L L H
Stand-by
Vcc ±
0.3V
X
X
Output Disable
L HH
Reset
X XX
Write
word L H L
byte L H L
Enable Block Group
Protect (3)
L
HL
Enable Block Group
Unprotect (3)
Temporary Block
Group
L
X
HL
XX
Auto Select
Manufacturer ID (5)
L
LH
Auto Select
Device Code (5)
L LH
H
L
X
X
X
H
L
X
X
X
X
X
WP/
ACC
L/H
(2)
L/H
L/H
(4)
L/H
(4)
(4)
L/H
L/H
A9 A6 A1 A0
A9 A6 A1 A0
A9 A6 A1 A0
X XXX
X XXX
X XXX
A9 A6 A1 A0
A9 A6 A1 A0
X LHL
X HHL
X XXX
VID L L L
VID L L H
DQ15/
A-1
DQ15
A-1
High-Z
High-Z
High-Z
DIN
A-1
X
X
X
X
X
DQ8/
DQ14
DOUT
High-Z
High-Z
High-Z
High-Z
DIN
High-Z
X
DQ0/
DQ7
DOUT
DOUT
High-Z
High-Z
High-Z
DIN
DIN
DIN
RESET
H
H
(2)
H
L
H
H
VID
X DIN VID
X X VID
X Code(See H
Table 9)
X
Code(See
Table 9)
H
Notes :
1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care.
2. WP/ACC and RESET pin are asserted at Vcc±0.3 V or Vss±0.3 V in the Stand-by mode.
3. Addresses must be composed of the Block address (A12 - A19).
The Block Protect and Unprotect operations may be implemented via programming equipment too.
Refer to the "Block Group Protection and Unprotection".
4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those
blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks
will be temporarily unprotected.
5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 9.
7 Revision 0.0
July 2004

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