74VHC00 - Quad 2-Input NAND Gate

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74VHC00 기능

기능

Quad 2-Input NAND Gate

제조업체

Fairchild Semiconductor

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February 2008

74VHC00

Quad 2-Input NAND Gate

Features

■ High Speed: tPD = 3.7ns (typ.) at TA = 25°C

■ High noise immunity: VNIH = VNIL = 28% VCC (min.)

■ Power down protection is provided on all inputs

■ Low noise: VOLP = 0.8V (max)

■ Low power dissipation: ICC = 2µA (max.) at TA = 25°C

■ Pin and function compatible with 74HC00

General Description

The VHC00 is an advanced high-speed CMOS 2-Input

NAND Gate fabricated with silicon gate CMOS technol-

ogy. It achieves the high-speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. The internal circuit is com-

posed of 3 stages, including buffer output, which provide

high noise immunity and stable output. An input protec-

tion circuit insures that 0V to 7V can be applied to the

input pins without regard to the supply voltage. This

device can be used to interface 5V to 3V systems and

two supply systems such as battery backup. This circuit

prevents device destruction due to mismatched supply

and input voltages.

Ordering Information

Order Number

Package

Number

Package Description

74VHC00M

74VHC00SJ

M14A

M14D

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC00MTC

74VHC00N

MTC14

N14A

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74VHC00 Rev. 1.3.0

www.fairchildsemi.com

DC Electrical Characteristics

Symbol Parameter

VIH HIGH Level Input

Voltage

VIL LOW Level Input

Voltage

VOH HIGH Level

Output Voltage

VOL LOW Level

Output Voltage

IIN Input Leakage

Current

ICC Quiescent

Supply Current

VCC (V)

2.0

Conditions

3.0–5.5

2.0

3.0–5.5

2.0 VIN = VIH IOH = –50µA

3.0 or VIL

4.5

3.0 IOH = –4mA

4.5 IOH = –8mA

2.0 VIN = VIH IOL = 50µA

3.0 or VIL

4.5

3.0

4.5

0–5.5

IOL = 4mA

IOL = 8mA

VIN = 5.5V or GND

5.5 VIN = VCC or GND

TA = 25°C

Min. Typ. Max.

TA = –40°C to

+85°C

Min. Max.

Units

1.50 1.50 V

0.7 x VCC

0.50

0.7 x VCC

0.50

0.3 x VCC

1.9 2.0

1.9

2.9 3.0

2.9

4.4 4.5

4.4

2.58 2.48

3.94 3.80

0.0 0.1

0.1 V

0.0 0.1

0.1

0.0 0.1

0.1

0.36 0.44

±0.1

±1.0

µA

2.0 20.0 µA

Noise Characteristics

Symbol

VOLP(2)

VOLV(2)

VIHD(2)

VILD(2)

Parameter

Quiet Output Maximum

Dynamic VOL

Quiet Output Minimum

Dynamic VOL

Minimum HIGH Level

Dynamic Input Voltage

Maximum LOW Level

Dynamic Input Voltage

Note:

2. Parameter guaranteed by design.

VCC (V)

Conditions

5.0 CL = 50pF

TA = 25°C

Typ.

Limits

0.3 0.8

–0.3 –0.8

3.5

1.5

Units

74VHC00 Rev. 1.3.0

www.fairchildsemi.com

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Physical Dimensions (Continued)

Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

74VHC00 Rev. 1.3.0

www.fairchildsemi.com

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사이트 맺음말

부품번호	상세설명 및 기능	제조사
74VHC00	QUAD 2-INPUT NAND GATE	STMicroelectronics
74VHC00	Quad 2-Input NAND Gate	Fairchild Semiconductor