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PDF MCM6209C Data sheet ( Hoja de datos )
| Número de pieza | MCM6209C | |
| Descripción | 64K x 4 Bit Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
64K x 4 Bit Fast Static RAM
With Output Enable
The MCM6209C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• Fast Access Times: 12, 15, 20, 25, and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
• Low Power Operation: 135 – 165 mA Maximum AC
• Fully TTL Compatible — Three–State Output
BLOCK DIAGRAM
A1
VCC
A2 VSS
A3
A4
A6
ROW
DECODER
MEMORY ARRAY
256 ROWS x
64 x 4 COLUMNS
A12
A13
A14
DQ0
INPUT
DQ1 DATA
CONTROL
DQ2
COLUMN I/O
COLUMN DECODER
DQ3
A0 A5 A7 A8 A9 A10 A11 A15
E
W
G
Order this document
by MCM6209C/D
MCM6209C
P PACKAGE
300 MIL PLASTIC
CASE 710B–01
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
NC 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
A9 11
E 12
G 13
VSS 14
28 VCC
27 A15
26 A14
25 A13
24 A12
23 A11
22 A10
21 NC
20 NC
19 DQ0
18 DQ1
17 DQ2
16 DQ3
15 W
PIN NAMES
A0 – A15 . . . . . . . . . . . . . Address Input
DQ0 – DQ3 . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
NC . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 3
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM6209C
1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
– 12 – 15 – 20 – 25 – 35
Parameter
Symbol Min Max Min Max Min Max Min Max Min Max Unit
Write Cycle Time
tAVAV 12 — 15 — 20 — 25 — 35 —
ns
Address Setup Time
Address Valid to End of Write
tAVWL 0 — 0 — 0 — 0 — 0 —
tAVWH 10 — 12 — 15 — 20 — 20 —
ns
ns
Write Pulse Width
tWLWH, 10 — 12 — 15 — 20 — 20 —
tWLEH
ns
Write Pulse Width, G High
tWLWH,
tWLEH
8
— 10 — 12 — 15 — 15 —
ns
Data Valid to End of Write
tDVWH 6 — 7 — 8 — 10 — 10 — ns
Data Hold Time
Write Low to Output High–Z
Write High to Output Active
tWHDX 0 — 0 — 0 — 0 — 0 — ns
tWLQZ 0 6 0 7 0 8 0 10 0 10 ns
tWHQX 4 — 4 — 4 — 4 — 4 — ns
Write Recovery Time
tWHAX 0 — 0 — 0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For Output Enable devices, if G goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. For Output Enable devices, if G ≥ VIH, the output will remain in a high impedance state
5. At any given voltage and temperature, tWLQZ max is less than tWHQX min, both for a given device and from device to device.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
Notes
3
4
5, 6, 7
5, 6, 7
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1 (W Controlled, See Note 2)
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLWH
tWLEH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6209C
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM6209C.PDF ] | |
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