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PDF MCM63P631TQ117 Data sheet ( Hoja de datos )
| Número de pieza | MCM63P631TQ117 | |
| Descripción | 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MCM63P631TQ117 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
64K x 32 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM63P631 is a 2M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the 68K Family, PowerPC™,
and Pentium™ microprocessors. It is organized as 64K words of 32 bits each.
This device integrates input registers, an output register, a 2–bit address counter,
and high speed SRAM onto a single monolithic circuit for reduced parts count in
cache data RAM applications. Synchronous design allows precise cycle control
with the use of an external clock (K). CMOS circuitry reduces the overall power
consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-
trolled through positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P631 (burst sequence op-
erates in linear or interleaved mode dependent upon state of LBO) and controlled
by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable SW are provided to allow writes to either individual bytes or to
all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P631 operates from a 3.3 V power supply, all inputs and outputs
are LVTTL compatible.
• MCM63P631–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)
MCM63P631–4.5 = 4.5 ns access / 10 ns cycle (100 MHz)
MCM63P631–7 = 7 ns access / 13.3 ns cycle (75 MHz)
MCM63P631–8 = 8 ns access / 15 ns cycle (66 MHz)
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• Sleep Mode (ZZ)
• PB1 Version 2.0 Compatible
• Single–Cycle Deselect Timing
• JEDEC Standard 100–Pin TQFP Package
Order this document
by MCM63P631/D
MCM63P631
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 3
8/4/97
M© OMoTtoOroRla,OInLc.A19F97AST SRAM
MCM63P631
1
1 page  
TRUTH TABLE (See Notes 1 through 5)
Next Cycle
Address
Used
SE1 SE2 SE3 ADSP ADSC ADV G 3
DQx
Write 2, 4
Deselect
None 1 X X X 0 X X High–Z
X
Deselect
None
0X1 0
X X X High–Z
X
Deselect
None
00X 0
X X X High–Z
X
Deselect
None
XX1 1
0 X X High–Z
X
Deselect
Begin Read
Begin Read
None
X0X
1
External
0
1
0
0
External
0
1
0
1
0 X X High–Z
X
X X X High–Z READ5
0 X X High–Z READ5
Continue Read
Next
XXX
1
1
0 1 High–Z READ
Continue Read
Next
XXX
1
1
0 0 DQ
READ
Continue Read
Next
1XX X
1 0 1 High–Z READ
Continue Read
Next
1XX X
1 0 0 DQ
READ
Suspend Read
Current X X X
1
1
1 1 High–Z READ
Suspend Read
Current X X X
1
1
1 0 DQ
READ
Suspend Read
Current 1 X X X 1 1 1 High–Z READ
Suspend Read
Current 1 X X X 1 1 0 DQ
READ
Begin Write
External
0
1
0
1
0 X X High–Z WRITE
Continue Write
Next
XXX
1
1
0 X High–Z WRITE
Continue Write
Next
1XX X
1 0 X High–Z WRITE
Suspend Write
Current X X X
1
1
1 X High–Z WRITE
Suspend Write
Current 1 X X X 1 1 X High–Z WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This READ assumes the RAM was previously deselected.
MOTOROLA FAST SRAM
MCM63P631
5
5 Page 
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MOTOROLA FAST SRAM
MCM63P631
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11 Page | ||
| Páginas | Total 16 Páginas | |
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