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PDF MCM63Z818TQ133 Data sheet ( Hoja de datos )
| Número de pieza | MCM63Z818TQ133 | |
| Descripción | 128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
128K x 36 and 256K x 18 Bit
Pipelined ZBT™ RAM
Synchronous Fast Static RAM
The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide
zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM63Z736 is organized
as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words
of 18 bits each, fabricated with high performance silicon gate CMOS
technology. This device integrates input registers, an output register, a 2–bit
address counter, and high speed SRAM onto a single monolithic circuit for
reduced parts count in communication applications. Synchronous design
allows precise cycle control with the use of an external clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (CK).
• 3.3 V LVTTL and LVCMOS Compatible
• MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Two–Cycle Deselect
• Byte Write Control
• ADV Controlled Burst
• 100–Pin TQFP Package
Order this document
by MCM63Z736/D
MCM63Z736
MCM63Z818
TQ PACKAGE
TQFP
CASE 983A–01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
2/6/98
©MMOoTtoOrolRa,OIncL.A19F98AST SRAM
MCM63Z736DMCM63Z818
1
1 page  
MCM63Z818 PIN DESCRIPTIONS
Pin Locations
85
89
87
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
86
31
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 80, 81, 82, 99, 100
36, 37
93, 94
(a) (b)
98
97
92
88
14, 15, 16, 41, 65, 66, 91
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 17, 21, 26, 40,
55, 60, 64, 67, 71, 76, 90
1, 2, 3, 6, 7, 25, 28, 29, 30,
38, 39, 42, 43, 51, 52, 53, 56, 57,
75, 78, 79, 83, 84, 95, 96
Symbol
ADV
CK
CKE
DQx
G
LBO
SA
SA0, SA1
SBx
SE1
SE2
SE3
SW
VDD
VDDQ
VSS
Type
Description
Input Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
Input Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Input Clock Enable: Disables the CK input when CKE is high.
I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
Input Asynchronous Output Enable.
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Input
Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
Input Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b) in conjunction with SW. Has no effect on read cycles.
Input Synchronous Chip Enable: Active low to enable chip.
Input Synchronous Chip Enable: Active high for depth expansion.
Input Synchronous Chip Enable: Active low for depth expansion.
Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
Supply Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
NC — No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
MCM63Z736DMCM63Z818
5
5 Page 
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 5%, TA = 0 to 70°C Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Supply Voltage
VDD
3.135
I/O Supply Voltage
Input Low Voltage
VDDQ*
VIL
3.135
– 0.3
Input High Voltage
VIH 2
Input High Voltage I/O Pins
VIH2
2
* VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels.
Typ
3.3
3.3
—
—
—
VIH
Max
3.465
VDD
0.8
VDD + 0.3
VDDQ + 0.3
Unit
V
V
V
V
V
VSS
VSS – 1.0 V
20% tKHKH (MIN)
Figure 5. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max Unit Notes
Input Leakage Current (0 V ≤ Vin ≤ VDD)
Output Leakage Current (0 V ≤ Vin ≤ VDDQ)
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max) Includes Supply Current for Both VDD and VDDQ
CMOS Standby Supply Current (Device Deselected,
Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS
Levels)
Ilkg(I)
Ilkg(O)
IDDA
ISB2
—
—
—
—
— ± 1 µA 1
— ± 1 µA
— 350 mA 2, 3, 4
— 5 mA 5, 6
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB3
—
—
25 mA 5, 7
Hold Supply Current (Device Selected, Freq = Max,
IDD1
—
—
15 mA 6
VDD = Max, VDDQ = Max, CKE ≥ VDD – 0.2 V, All Inputs Static at
CMOS Levels)
Output Low Voltage (IOL = 8 mA)
VOL
—
—
0.4 V
Output High Voltage (IOH = – 8 mA)
VOH
2.4
—
—V
NOTES:
1. LBO has an internal pullup and will exhibit leakage currents of ± 5 µA.
2. Reference AC Operating Conditions and Characteristics for Input and Timing.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Device in deselected mode as defined by the Truth Table.
6. CMOS levels for I/Os are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
7. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Input Capacitance
Input/Output Capacitance
Cin
CI/O
—
—
4
7
Max Unit
5 pF
8 pF
MOTOROLA FAST SRAM
MCM63Z736DMCM63Z818
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MCM63Z818TQ133.PDF ] | |
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