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PDF MCM64PD32 Data sheet ( Hoja de datos )
| Número de pieza | MCM64PD32 | |
| Descripción | 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
256K/512K Pipelined BurstRAM™
Secondary Cache Module
for Pentium™
The MCM64PD32 (256K) and MCM64PD64 (512K) are designed to provide
a burstable, high performance, L2 cache for the Pentium microprocessor in
conjunction with Intel’s Triton II chip set. The MCM64PD32 is configured as 32K
x 64 bits and the MCM64PD64 is configured as 64K x 64 bits. Both are packaged
in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K
x 32 BurstRAMs and two Motorola 3.3 V 32K x 8 FSRAM for the tag RAM.
Bursts can be initiated with either address status processor (ADSP) or cache
address status (CADS). Subsequent burst addresses are generated internal to
the BurstRAM by the cache burst advance (CADV) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLK0) input. Eight write enables are provided for byte write control.
PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache
control.
• Pentium–Style Burst Counter on Chip
• Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rate: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM
8 ns for Data RAMs
• One–cycle Deselect Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
• Single 3.3 V +10%, – 5% Power Supply
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Intel COAST 3.0 Option III Compliant
• Burst Order Select (BOSEL) Option
Order this document
by MCM64PD32/D
MCM64PD32
MCM64PD64
160–LEAD CARD EDGE
CASE TBD, TOP VIEW
1
42
43
80
BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
6/14/96
M© OMoTtoOroRla,OInLc.A19F96AST SRAM
MCM64PD32•MCM64PD64
1
1 page  
PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations
20, 21, 22, 23, 24, 26, 28, 29,
101, 102, 103, 104, 106, 108, 109, 110
30
114
18
9
89
16
91
36, 116
11, 12, 13, 14, 92, 93, 94, 96
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
31, 32
17
33, 34, 112, 113
2, 3, 4, 5, 6, 82, 83, 84, 85, 86, 88
8
7, 15, 25, 39, 52, 60, 68, 76
87, 95, 105, 119, 132, 140, 148, 156
1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,
136, 144, 152, 160
100, 111
97, 98
Symbol
A3 – A18
ADSP
BOSEL
BWE
CADS
CADV
CCS
CG
CLK0,
CLK1
CWE0 –
CWE7
DQ0 –
DQ63
ECS1,
ECS2
GWE
PD0 –
PD3
TIO0 –
TIO10
TWE
VDD3
VDD5
VSS
RSVD
NC
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Address Inputs: These inputs are registered into data RAMs and must
meet setup and hold times. The tag RAM addresses are not registered.
Address Status Processor: Initiates READ, WRITE, or chip deselect
cycle (Exception–chip deselect dGs not occur when ADSP is asserted
and CCS is high.
Burst Order Select: NC for interleaved burst counter. Tie to ground for
linear burst counter.
Byte Write Enable: To be used in future modules.
Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.
Cache Burst Advance: Increments address count in accordance with
interleaved count style.
Chip Select: Active low chip enable for data RAMs.
Cache Output Enable: Active low asynchronous input.
Low – enables output buffers (DQ pins)
High – DQx pins are high impedance.
Clock: This signal registers the address, data in, and all control signals
except CG.
Cache Data Byte Write Enable: Active low write signal for data RAMs.
I/O Synchronous Data I/O:
Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.
Input Expansion Chip Select
Input
—
Global Write Enable: To be used in future modules.
Presence Detect: See Presence Detect Table
I/O Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
Input Tag Write Enable: Active low write signal for tag RAMs.
Supply Power Supply: 3.3 V + 10%, – 5%.
Supply Power Supply: 5.0 V ± 5%.
Supply Ground.
— No Connection: Reserved for future use.
— No Connection: There is no connection to the module.
MOTOROLA FAST SRAM
MCM64PD32•MCM64PD64
5
5 Page 
MOTOROLA FAST SRAM
MCM64PD32•MCM64PD64
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MCM64PD32.PDF ] | |
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