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PDF MCM6706CRJ5.5R Data sheet ( Hoja de datos )
| Número de pieza | MCM6706CRJ5.5R | |
| Descripción | 32K x 8 Bit Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MCM6706CRJ5.5R (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6706CR/D
Product Preview
32K x 8 Bit Static Random
Access Memory
The MCM6706CR is a 262,144 bit static random access memory organized
as 32,768 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706CR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 32–lead surface–mount SOJ package.
• Single 5.0 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: MCM6706CR–5 = 5 ns
MCM6706CR–5.5 = 5.5 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A
A VCC
VSS
A
A MEMORY
A
ROW
MATRIX
DECODER
512 ROWS x 64 x 8
A COLUMNS
A
A
A
DQ0 COLUMN I/O
INPUT
DATA
COLUMN DECODER
CONTROL
DQ7
A AA A AA
E
W
G
MCM6706CR
J PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
A1
A2
A3
A4
E5
DQ 6
DQ 7
VCC 8
VSS 9
DQ 10
DQ 11
W 12
A 13
A 14
A 15
A 16
32 NC
31 A
30 A
29 A
28 G
27 DQ
26 DQ
25 VSS
24 VCC
23 DQ
22 DQ
21 A
20 A
19 A
18 A
17 NC
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address
W . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . . No Connection
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
10/9/96
M© OMoTtoOroRla,OInLc.A19F96AST SRAM
MCM6706CR
1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706CR–5
MCM6706CR–5.5
Parameter
Symbol
Min
Max
Min
Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
5
0
6
6
—
5.5
— ns
3
— 0 — ns
— 6 — ns
— 6 — ns
Data Valid to End of Write
tDVWH
3.5
—
3
— ns
Data Hold Time
tWHDX
0
—
0
— ns
Write Low to Data High–Z
tWLQZ
—
3.5
—
3.5 ns 4, 5, 6
Write High to Output Active
tWHQX
3
—
3
— ns 4, 5, 6
Write Recovery Time
tWHAX
0
—
0
— ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWL
HIGH–Z
tWLQZ
tAVWH
tWLEH
tWLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6706CR
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM6706CRJ5.5R.PDF ] | |
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