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PDF MCM6709AJ8R2 Data sheet ( Hoja de datos )
| Número de pieza | MCM6709AJ8R2 | |
| Descripción | 64K x 4 Bit Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6709A/D
64K x 4 Bit Static RAM
The MCM6709A is a 262,144 bit static random access memory organized as
65,536 words of 4 bits, fabricated using high–performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G) provides increased system flexibility and eliminates bus
contention problems.
The MCM6709A is available in a 300 mil, 28 lead plastic surface–mount SOJ
package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Fast Access Times:
MCM6709A–8 = 8 ns
MCM6709A–10 = 10 ns
MCM6709A–12 = 12 ns
BLOCK DIAGRAM
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
256 ROWS x 256 x 4
COLUMNS
A
A
A
DQ0
•••
•••
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
•••
DQ3
AA A A AAAA
E
W
G
MCM6709A
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
NC 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
A9 11
E 12
G 13
VSS 14
28 VCC
27 A15
26 A14
25 A13
24 A12
23 A11
22 A10
21 NC
20 NC
19 DQ0
18 DQ1
17 DQ2
16 DQ3
15 W
PIN NAMES
A0 – A15 . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ0 – DQ3 . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . No Connection
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM6709A
2–1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6709A–8 MCM6709A–10 MCM6709A–12
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time
tAVAV
8
— 10 — 12 — ns 3
Address Setup Time
tAVWL
0
—
0
—
0
— ns
Address Valid to End of Write
tAVWH
8
—
9
— 10 — ns
Write Pulse Width
tWLWH,
8
—
9
— 10 — ns
tWLEH
Data Valid to End of Write
tDVWH
4
—
5
—
6
— ns
Data Hold Time
tWHDX
0
—
0
—
0
— ns
Write Low to Data High–Z
tWLQZ
0
4
0
5
0
6 ns 4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
— ns 4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
— ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLWH
tWLEH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6709A
2–5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM6709AJ8R2.PDF ] | |
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