PDF MCM6709BJ12R Data sheet ( Hoja de datos )

Número de pieza	MCM6709BJ12R
Descripción	64K x 4 Bit Static RAM
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 64K x 4 Bit Static RAM The MCM6709B is a 262,144 bit static random access memory organized as 65,536 words of 4 bit. Static design eliminates the need for external clocks or tim- ing strobes. Output enable (G), a special control feature of the MCM6709B, provides in- creased system flexibility and eliminates bus contention problems. The MCM6709B is available in a 300 mil, 28 lead plastic surface–mount SOJ package. • Single 5 V ± 10% Power Supply • Fully Static — No Clock or Timing Strobes Necessary • All Inputs and Outputs are TTL Compatible • Three State Outputs • Fast Access Times: MCM6709B–8 = 8 ns MCM6709B–10 = 10 ns MCM6709B–12 = 12 ns BLOCK DIAGRAM A A A A A ROW DECODER ••• MEMORY MATRIX 256 ROWS x 256 x 4 COLUMNS A A A DQ ••• ••• INPUT DATA CONTROL COLUMN I/O COLUMN DECODER ••• DQ AA A A AAAA E W G Order this document by MCM6709B/D MCM6709B J PACKAGE 300 MIL SOJ CASE 810B–03 PIN ASSIGNMENT NC 1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11 E 12 G 13 VSS 14 28 VCC 27 A 26 A 25 A 24 A 23 A 22 A 21 NC 20 NC 19 DQ 18 DQ 17 DQ 16 DQ 15 W PIN NAMES A . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . Chip Enable DQ . . . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . No Connection This document contains informantion on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 1 10/9/96 M© OMoTtoOroRla,OInLc.A19F96AST SRAM MCM6709B 1 1 page WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) MCM6709B–8 MCM6709B–10 MCM6709B–12 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 8 — 10 — 12 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 8 — 9 — 10 — ns Write Pulse Width tWLWH 8 — 9 — 10 — ns tWLEH Data Valid to End of Write tDVWH 4 — 5 — 6 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ — 4 — 5 — 6 ns 4, 5, 6 Write High to Output Active tWHQX 3 — 3 — 3 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady state voltage with load of Figure 1b. 5. This parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) WRITE CYCLE 1 tAVAV tAVWL HIGH–Z tAVWH tWLQZ tWLWH tWLEH tDVWH DATA VALID HIGH–Z tWHAX tWHDX tWHQX MOTOROLA FAST SRAM MCM6709B 5 5 Page

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