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PDF MCM6709RJ6R2 Data sheet ( Hoja de datos )
| Número de pieza | MCM6709RJ6R2 | |
| Descripción | 64K x 4 Bit Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
64K x 4 Bit Static RAM
The MCM6709R is a 262,144 bit static random access memory organized as
65,536 words of 4 bits, fabricated using high–performance silicon–gate BiCMOS
technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6709R meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 28 lead plastic surface–mount SOJ package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs are TTL Compatible
• Center Power and I/O Pins for Reduced Noise
• Three State Outputs
• Fast Access Times: MCM6709R–6 = 6 ns
MCM6709R–7 = 7 ns
MCM6709R–8 = 8 ns
BLOCK DIAGRAM
A
A
A
A
A
A
ROW
DECODER
•••
MEMORY MATRIX
512 ROWS x 128 x 4
COLUMNS
A
A
A
DQ0
•••
•••
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
•••
DQ3
AA A AAA A
E
W
G
Order this document
by MCM6709R/D
MCM6709R
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
A0 1
A1 2
A2 3
A3 4
E5
DQ0 6
VCC 7
VSS 8
DQ1 9
W 10
A4 11
A5 12
A6 13
A7 14
28 A15
27 A14
26 A13
25 A12
24 G
23 DQ3
22 VSS
21 VCC
20 DQ2
19 A11
18 A10
17 A9
16 A8
15 NC
PIN NAMES
A0 – A15 . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ0 – DQ3 . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must
be connected for proper operation of the
device.
REV 1
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM6709R
1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6709R–6
MCM6709R–7
MCM6709R–8
Parameter
Symbol
Min
Max
Min
Max
Min
Max Unit Notes
Write Cycle Time
tAVAV
6
—
7
—
8
— ns 3
Address Setup Time
Address Valid to End of Write
tAVWL
0
—
0
—
0
— ns
tAVWH
6
—
7
—
8
— ns
Write Pulse Width
tWLWH,
6
—
7
—
8
— ns
tWLEH
Data Valid to End of Write
tDVWH
3
— 3.5 —
4
— ns
Data Hold Time
Write Low to Data High–Z
tWHDX
tWLQZ
0
0
—
3.5
0—0
0 3.5 0
— ns
4 ns 4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
— ns 4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
— ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLWH
tWLEH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6709R
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM6709RJ6R2.PDF ] | |
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