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부품번호 | 74VHC175 기능 |
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기능 | Quad D-Type Flip-Flop | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 7 페이지수
August 1993
Revised April 1999
74VHC175
Quad D-Type Flip-Flop
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: fMAX = 210 MHz (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.8V (max)
s Pin and function compatible with 74HC175
Ordering Code:
Order Number Package Number
Package Description
74VHC175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC175MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D3
CP
MR
Q0–Q3
Q0–Q 3
Description
Data Inputs
Clock Pulse Input
Master Reset Input
True Outputs
Complement Outputs
Logic Symbols
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS011637.prf
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = 25°C
TA = −40°C to +85°C
Units
(V) Min Typ Max Min Max
Conditions
fMAX
Maximum Clock
Frequency
3.3 ± 0.3
90
50
140
75
75 MHz CL = 15 pF
45 CL = 50 pF
5.0 ± 0.5
150
85
210
115
125 MHz CL = 15 pF
75 CL = 50 pF
tPLH Propagation Delay
3.3 ± 0.3
tPHL Time (CP to Qn or Qn)
7.5
11.5
1.0
13.5
ns CL = 15 pF
10.0
15.0
1.0
17.0
CL = 50 pF
5.0 ± 0.5
4.8 7.3 1.0 8.5 ns CL = 15 pF
6.3 9.3 1.0 10.5
CL = 50 pF
tPLH
Propagation Delay Time
3.3 ± 0.3
tPHL
(MR to Qn or Qn)
6.3
10.1
1.0
12.0
ns CL = 15 pF
8.8 13.6 1.0 15.5
CL = 50 pF
5.0 ± 0.5
4.3 6.4 1.0 7.5 ns CL = 15 pF
5.8 8.4 1.0 9.5
CL = 50 pF
tOSLH
Output to
3.3 ± 0.3
1.5 1.5 CL = 50 pF
tOSHL
Output Skew
5.0 ± 0.5
1.0 1.0 CL = 50 pF
(Note 4)
CIN Input Capacitance
CPD Power Dissipation
Capacitance
4 10
44
10 pF VCC = Open
pF (Note 5)
Note 4: Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL =| tPHLmax − tPHLmin|.
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can
be calculated by the following equation: CPD (total) = 30 + 14 • n
AC Operating Requirements
Symbol
Parameter
tW(L)
tW(H)
tW(L)
Minimum Pulse Width (CP)
Minimum Pulse Width (MR)
tS Minimum Setup Time (Dn to CP)
tH Minimum Hold Time (Dn to CP)
tREC
Minimum Removal Time (MR)
Note 6: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V
VCC
(V)
(Note 6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = 25°C
TA = −40°C to +85°C
Typ Guaranteed Minimum
5.0 5.0
5.0 5.0
5.0 5.0
5.0 5.0
5.0 5.0
4.0 4.0
1.0 1.0
1.0 1.0
5.0 5.0
5.0 5.0
Units
ns
ns
ns
ns
ns
www.fairchildsemi.com
4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
7페이지 | |||
구 성 | 총 7 페이지수 | ||
다운로드 | [ 74VHC175.PDF 데이터시트 ] |
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