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부품번호 | 74VHC273M 기능 |
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기능 | OCTAL D-TYPE FLIP FLOP WITH CLEAR | ||
제조업체 | STMicroelectronics | ||
로고 | |||
전체 10 페이지수
® 74VHC273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 165 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHC273 is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP WITH
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
technology.
PRELIMINARY DATA
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC273M
74VHC273T
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs .
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
October 1999
1/10
74VHC273
AC ELECTRICAL CHARACTERISTICS (Input tr = tf =3 ns)
Symb ol
Parameter
Test Condition
V CC
( V)
CL
(pF)
tPLH Propagation Delay
tPHL Time
CK to Q
tPHL Propagation Delay
Time
CLR to Q
tw CLR pulse Width
LOW
3.3(*)
3.3(*)
5.0(**)
5.0(**)
3.3(*)
3.3(*)
5.0(**)
5.0(**)
3.3(*)
5.0(**)
15
50
15
50
15
50
15
50
tw CK pulse Width
HIGH or LOW
3.3(*)
5.0(**)
ts Setup Time D to CK
HIGH or LOW
3.3(*)
5.0(**)
th Hold Time D to CK
HIGH or LOW
3.3(*)
5.0(**)
tREM Removal Time
CLR to CK
3.3(*)
5.0(**)
fMAX Maximum Clock
Frequency
3.3(*)
3.3(*)
15
50
5.0(**)
15
5.0(**)
50
tOSLH Output to Output Skew
tOSHL Time (note 1)
3.3(*)
5.0(**)
50
50
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5V ± 0.5V
Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn|
Value
TA = 25 oC
Min. Typ. Max.
8.7 13.6
11.2 17.1
5.8 9.0
7.3 11.0
8.9 13.6
11.4 17.1
5.2 8.5
6.7 10.5
5.0
5.0
5.5
5.0
5.5
4.5
1.0
1.0
2.5
2.0
75 120
50 75
120 165
80 110
1.5
1.0
-40 to 85 oC
Min . Max.
1.0 16.0
1.0 19.5
1.0 10.5
1.0 12.5
1.0 16.0
1.0 19.5
1.0 10.0
1.0 12.0
6.0
5.0
6.5
5.0
6.5
4.5
1.0
1.0
2.5
2.0
65
45
100
70
1.5
1.0
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
Value
Un it
TA = 25 oC
-40 to 85 oC
Min. Typ . Max. Min . Max.
CIN Input Capacitance
4 10
10 pF
CPD Power Dissipation
Capacitance (note 1)
31 pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/8 (per Flip-Flop)
4/10
4페이지 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74VHC273
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
7/10
7페이지 | |||
구 성 | 총 10 페이지수 | ||
다운로드 | [ 74VHC273M.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
74VHC273 | OCTAL D-TYPE FLIP FLOP WITH CLEAR | STMicroelectronics |
74VHC273 | Octal D-Type Flip-Flop | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |