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74VHC273M 데이터시트 PDF




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부품번호 74VHC273M 기능
기능 Octal D-Type Flip-Flop
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74VHC273M 데이터시트, 핀배열, 회로
April 1994
Revised April 1999
74VHC273
Octal D-Type Flip-Flop
General Description
The VHC273 is an advanced high speed CMOS Octal D-
type flip-flop fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
The register has a common buffered Clock (CP) which is
fully edge-triggered. The state of each D input, one setup
time before the LOW-to-HIGH clock transition, is trans-
ferred to the corresponding flip-flop’s Q output. The Master
Reset (MR) input will clear all flip-flops simultaneously. All
outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input.
An input protection circuit insures that 0V to 7V can be
applied to the inputs pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: fMAX= 165 MHz (typ) at VCC = 5V
s Low power dissipation: ICC = 4 µA (max) at TA = 25°C
s High noise immunity: VNIH = VNIL = 28% VCC (min)
s Power down protection is provided on all inputs
s Low noise: VOLP = 0.9V (max)
s Pin and function compatible with 74HC273
Ordering Code:
Order Number Package Number
Package Description
74VHC273M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHC273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC273N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
© 1999 Fairchild Semiconductor Corporation DS011670.prf
www.fairchildsemi.com




74VHC273M pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = 25°C
TA = −40°C to +85°C
Units
(V) Min Typ Max Min Max
Conditions
fMAX
tPLH
tPHL
tPHL
Maximum Clock
Frequency
3.3 ± 0.3
75
50
120
75
65
MHz
45
5.0 ± 0.5
120
80
165
110
100
MHz
70
Propagation Delay
Time (CK - Q)
3.3 ± 0.3
8.7 13.6 1.0 16.0
ns
11.2 17.1 1.0 19.5
5.0 ± 0.5
5.8 9.0 1.0 10.5
ns
7.3 11.0 1.0 12.5
Propagation Delay
Time (MR - Q)
3.3 ± 0.3
8.9 13.6 1.0 16.0
ns
11.4 17.1 1.0 19.5
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
tOSLH
tOSHL
CIN
CPD
Output to
Output Skew
Input Capacitance
Power Dissipation
Capacitance
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
5.2 8.5 1.0 10.0
ns
6.7 10.5 1.0 12.0
CL = 15 pF
CL = 50 pF
1.5
1.5
(Note 4)
ns
CL = 50 pF
1.0 1.0
CL = 50 pF
4 10
10 pF VCC = Open
31 (Note 5)
pF
Note 4: Parameter guaranteed by design tOSLH = |tPLHmax tPLHmin|; tOSHL = |tPHLmax tPHLmin|.
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per F/F). The total CPD when n pieces of the Flip Flop operates can
be calculated by the equation: CPD (total) = 22 + 9n.
AC Operating Requirements
Symbol
Parameter
tW(L)
tW(H)
tW(L)
Minimum Pulse Width (CK)
Minimum Pulse Width (MR)
tS
tH
tREC
Minimum Setup Time
Minimum Hold Time
Minimum Removal Time (MR)
Note 6: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V
VCC
(V)
(Note 6)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = 25°C
TA = −40°C to +85°C
Typ Guaranteed Minimum
5.5 6.5
5.0 5.0
5.0 6.0
5.0 5.0
5.5 6.5
4.5 4.5
1.0 1.0
1.0 1.0
2.5 2.5
2.0 2.0
Units
ns
ns
ns
ns
ns
www.fairchildsemi.com
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74VHC273M 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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