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74VHC373 데이터시트 PDF




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부품번호 74VHC373 기능
기능 Octal D-Type Latch with 3-STATE Outputs
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74VHC373 데이터시트, 핀배열, 회로
February 1993
Revised April 1999
74VHC373
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC373 is an advanced high speed CMOS octal D-
type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latch enable input (LE) and an out-
put enable input (OE). The latches appear transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is LATCHED. When the OE
input is HIGH, the eight outputs are in a high impedance
state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s High Speed: tPD = 5.0 ns (typ) @ VCC = 5V
s High Noise Immunity: VNIH = VNIL = 28% VCC (Min)
s Power Down Protection is provided on all inputs
s Low Noise: VOLP = 0.6V (typ)
s Low Power Dissipation: ICC = 4 µA (Max) @ TA = 25°C
s Pin and Function Compatible with 74HC373
Ordering Code:
Order Number Package Number
Package Description
74VHC373M
74VHC373SJ
74VHC373MTC
M20B
M20D
MTC20
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011555.prf
www.fairchildsemi.com




74VHC373 pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
Units
(V) Min Typ Max Min Max
Conditions
tPLH
tPHL
tPLH
tPHL
tPZL
tPZH
tPLZ
tPHZ
tOSLH
tOSHL
CIN
COUT
CPD
Propagation Delay
Time (LE to On)
Propagation Delay
Time (D to On)
3-STATE
Output
Enable Time
3-STATE Output
Disable Time
Output to
Output Skew
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
7.0 11.0 1.0 13.0
ns
9.5 14.5 1.0 16.5
CL = 15 pF
CL = 50 pF
4.9 7.2 1.0 8.5
ns
6.4 9.2 1.0 10.5
CL = 15 pF
CL = 50 pF
7.3 11.4 1.0 13.5
CL = 15 pF
9.8 14.9 1.0 17.0
ns
5.0 7.2 1.0 8.5
CL = 50 pF
CL = 15 pF
6.5 9.2 1.0 10.5
CL = 50 pF
7.3
11.4
1.0
13.5
ns RL = 1 k
CL = 15 pF
9.8 14.9 1.0 17.0
CL = 50 pF
5.5 8.1 1.0 9.5
ns
7.0 10.1 1.0 11.5
CL = 15 pF
CL = 50 pF
9.5
13.2
1.0
15.0
ns RL = 1 k
CL = 50 pF
6.5 9.2 1.0 10.5
CL = 50 pF
1.5
1.5
(Note 4)
ns
CL = 50 pF
1.0 1.0
CL = 50 pF
4 10
10 pF VCC = Open
6 pF VCC = 5.0V
27 pF (Note 5)
Note 4: Parameter guaranteed by design. tOSLH = |tPLH max tPLH min |; tOSHL = |tPHL max tPHL min|
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC/8 (per Latch). The total CPD when n pcs. of the Latch operates can be
calculated by the equation: CPD(total) = 14 + 13n.
AC Operating Requirements
Symbol
Parameter
tW(H)
Minimum Pulse Width (LE)
tS Minimum Set-Up Time
tH Minimum Hold Time
VCC
(V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
TA = +25°C
Min Typ Max
5.0
5.0
4.0
4.0
1.0
1.0
TA = −40°C to +85°C
Min Max
5.0
5.0
4.0
4.0
1.0
1.0
Units
ns
ns
ns
www.fairchildsemi.com
4

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74VHC373 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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