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74VHC4046M 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 74VHC4046M은 전자 산업 및 응용 분야에서
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부품번호 74VHC4046M 기능
기능 CMOS Phase Lock Loop
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74VHC4046M 데이터시트, 핀배열, 회로
www.DataSheet4U.com
April 1994
Revised October 2003
74VHC4046
CMOS Phase Lock Loop
General Description
The VHC4046 is a low power phase lock loop utilizing
advanced silicon-gate CMOS technology to obtain high fre-
quency operation both in the phase comparator and VCO
sections. This device contains a low power linear voltage
controlled oscillator (VCO), a source follower, and three
phase comparators. The three phase comparators have a
common signal input and a common comparator input. The
signal input has a self biasing amplifier allowing signals to
be either capacitively coupled to the phase comparators
with a small signal or directly coupled with standard input
logic levels. This device is similar to the CD4046 except
that the Zener diode of the metal gate CMOS device has
been replaced with a third phase comparator.
Phase Comparator I is an exclusive OR (XOR) gate. It pro-
vides a digital error signal that maintains a 90 phase shift
between the VCO’s center frequency and the input signal
(50% duty cycle input waveforms). This phase detector is
more susceptible to locking onto harmonics of the input fre-
quency than phase comparator I, but provides better noise
rejection.
Phase comparator III is an SR flip-flop gate. It can be used
to provide the phase comparator functions and is similar to
the first comparator in performance.
Phase comparator II is an edge sensitive digital sequential
network. Two signal outputs are provided, a comparator
output and a phase pulse output. The comparator output is
a 3-STATE output that provides a signal that locks the VCO
output signal to the input signal with 0 phase shift between
them. This comparator is more susceptible to noise throw-
ing the loop out of lock, but is less likely to lock onto har-
monics than the other two comparators.
In a typical application any one of the three comparators
feed an external filter network which in turn feeds the VCO
input. This input is a very high impedance CMOS input
which also drives the source follower. The VCO’s operating
frequency is set by three external components connected
to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided
to disable the VCO and the source follower, providing a
method of putting the IC in a low power state.
The source follower is a MOS transistor whose gate is con-
nected to the VCO input and whose drain connects the
Demodulator output. This output normally is used by tying
a resistor from pin 10 to ground, and provides a means of
looking at the VCO input without loading down modifying
the characteristics of the PLL filter.
Features
s Low dynamic power consumption: (VCC = 4.5V)
s Maximum VCO operating frequency: 12 MHz
(VCC = 4.5V)
s Fast comparator response time (VCC = 4.5V)
Comparator I: 25 ns
Comparator II: 30 ns
Comparator III: 25 ns
s VCO has high linearity and high temperature stability
s Pin and function compatible with the 74HC4046
Ordering Code:
Order Number Package Number
Package Description
74VHC4046M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC4046MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC4046N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2003 Fairchild Semiconductor Corporation DS011675
www.fairchildsemi.com




74VHC4046M pdf, 반도체, 판매, 대치품
AC Electrical Characteristics VCC = 2.0 to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified.)
Symbol
Parameters
AC Coupled
Input Sensitivity,
Signal In
tr, tf Maximum Output
Rise and Fall Time
Conditions
C (series) = 100 pF
fIN = 500 kHz
CIN Maximum Input
Capacitance
Phase Comparator I
tPHL, tPLH Maximum Propagation
Delay
Phase Comparator II
tPZL Maximum 3-STATE
Enable Time
tPZH, tPHZ Maximum 3-STATE
Enable Time
tPLZ Maximum 3-STATE
Disable Time
tPHL, tPLH Maximum Propagation
Delay HIGH-to-LOW
to Phase Pulses
Phase Comparator III
tPHL, tPLH Maximum Propagation
Delay
CPD Maximum Power
Dissipation
Capacitance
All Comparators
VIN = VCC and GND
VCC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
7
TA=25C
TA=−40 to 85°C
Typ Guaranteed Limits
25 100
150
50 150
200
135 250
300
30 75
95
9 15
19
8 12
15
Units
mV
mV
mV
ns
ns
ns
pF
3.3V
4.5V
6.0V
3.3V
4.5V
6.0V
3.3V
4.5V
6.0V
3.3V
4.5V
6.0V
3.3V
4.5V
6.0V
3.3V
4.5V
6.0V
65
25
20
75
25
22
88
30
25
90
32
28
100
34
27
75
25
22
130
117
40
34
130
45
38
140
48
41
140
48
41
146
50
43
117
40
34
146 ns
50 ns
43 ns
160 ns
56 ns
48 ns
175 ns
60 ns
51 ns
175 ns
60 ns
51 ns
180 ns
63 ns
53 ns
146 ns
50 ns
43 ns
pF
Voltage Controlled Oscillator (Specified to operate from VCC = 3.0V to 6.0V)
fMAX
Maximum
Operating
Frequency
Duty Cycle
C1 = 50 pF
R1 = 100
R2 = ∞
VCOin = VCC
C1 = 0 pF
R1 = 100
VCOin = VCC
4.5V
6.0V
4.5V
6.0
Demodulator Output
Offset Voltage
VCOinVdem
Offset
Variation
Rs = 20 k
Rs = 20 k
VCOin = 1.75V
2.25V
4.5V
4.5V
2.75V
7
11
12
14
50
0.75
0.65
0.1
0.75
4.5
7
1.3
MHz
MHz
MHz
MHz
%
1.5 V
V
www.fairchildsemi.com
4

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74VHC4046M 전자부품, 판매, 대치품
Typical Performance Characteristics (Continued)
VHC4046 VCOOUT vs
Temperature VCC = 4.5V
VHC4046 VCOOUT vs
Temperature VCC = 6V
VHC4046 Typical Source Follower
Power Dissipation vs RS
Typical fMAX/fMIN vs R2/R1
VCC = 4.5V & 6V fMAX/fMIN
7 www.fairchildsemi.com

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관련 데이터시트

부품번호상세설명 및 기능제조사
74VHC4046

CMOS Phase Lock Loop

Fairchild Semiconductor
Fairchild Semiconductor
74VHC4046M

CMOS Phase Lock Loop

Fairchild Semiconductor
Fairchild Semiconductor

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