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PDF MB1501L Data sheet ( Hoja de datos )
| Número de pieza | MB1501L | |
| Descripción | SERIAL INPUT PLL FREQUENCY SYNTHESIZER | |
| Fabricantes | Fujitsu | |
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September 1995
Edition 6.0a
DATA SHEET
MB1501/MB1501H/MB1501L
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 1.1GHz PRESCALER
The Fujitsu MB1501/MB1501H/MB1501L, utilizing BI-CMOS technology, is a
single chip serial input PLL frequency synthesizer with pulse-swallow function.
The MB1501 series contain a 1.1GHz two modulus prescaler that can select either
64/65 or 128/129 divide ratio; control signal generator; 16-bit shift register; 15-bit
latch; programmable reference divider (binary 14-bit programmable reference
counter); 1-bit switch counter; phase comparator with phase inverse function;
charge pump; crystal oscillator; 19-bit shift register; 18-bit latch; programmable
divider (binary 7-bit swallow counter and binary 11-bit programmable counter).
The MB1501 operates on a low supply voltage (3V typ) and consumes low power
(45mW at 1.1GHz).
PLASTIC PACKAGE
DIP-16P-M04
MB1501 Product Line
VP VOOP
Voltage Voltage
Lock up
time
MB1501 8V max 8.5V max Middle speed
MB1501H 10V max 10.0V max High speed
MB1501L 8V max 8.5V max Low speed
DO
Output
Width
Middle
Low
High
High-level Low-level
Output Output
Current Current
Middle Middle
High
Low
Low High
• High operating frequency: fIN MAX=1.1GHz (PIN MIN=0.20VP-P)
• On-chip prescaler
• Low power supply voltage: 2.7V to 5.5V (3.0V typ)
• Low power supply consumption: 45mW (3.0V, 1.1GHz operation)
• Serial input 18-bit programmable divider consisting of:
Binary 7-bit swallow counter (Divide ratio: 0 to 127)
Binary 11-bit programmable counter (Divide ratio: 16 to 2047)
• Serial input 15-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter (Divide ratio: 8 to 16383)
1-bit switch counter (SW) Sets divide ratio of prescaler
• 2types of phase detector output
On-chip charge pump (Bipolar type)
Output for external charge pump
• Wide operating temperature: TA=–40°C to +85°C
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Symbol Condition
Value
Unit
Power Supply Voltage
Output Voltage
Open-drain Output
Output Current
Storage Temperature
VCC
VPH
VP,VPL
VOUT
VOOPH
VOOP,VOOPL
IOUT
TSTG
MB1501H
MB1501/1501L
MB1501H
MB1501/1501L
–0.5 to +7.0
VCC to 12.0
VCC to 10.0
–0.5 to VCC +0.5
–0.5 to 11.0
–0.5 to 9.0
±10
–55 to +125
V
V
V
V
mA
°C
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PLASTIC PACKAGE
FPT-16P-M06
PIN ASSIGNMENT
OSCIN 1
OSCOUT 2
16 ØR
15 ØP
VP 3
14 fP
VCC 4
13 fr
DO 5 ( TOP VIEW ) 12 FC
GND 6
11 LE
LD 7
10 Data
fin 8
9 Clock
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. How-
ever, it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated volt-
ages to this high impedance circuit.
©Copyright 1994 by FUJITSU LIMITED and FUJITSU MICROELECTRONICS, INC.
1
1 page  
MB1501
MB1501H
MB1501L
FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown below.
Last data input
Control bit
LSB
Data input
First data input
MSB
SSSSSSSSSSSSSSSSSS
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Divide ratio of swallow counter
setting bits
Divide ratio of programmable counter
setting bits
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide S S S S S S S
ratio
A 7654321
0 0000000
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
ratio
N
SSSSSSSSS
18 17 16 15 14 13 12 11 10
S
9
16 0 0 0 0 0 0 1 0 0 0
S
8
0
1 0000001
17 0 0 0 0 0 0 1 0 0 0 1
• •••••••
• •••••••••••
127 1 1 1 1 1 1 1
2047 1 1 1 1 1 1 1 1 1 1 1
Divide ratio A : 0 to 127
Divide ratio less than 16 is prohibited.
Divide ratio N : 16 to 2047
S8 to S18 :Divide ratio of programmable counter setting bits (16 to 2047)
S1 to S7 : Divide ratio of swallow counter setting bits (0 to 127)
C: Control bit (Control bit is set to low.)
Dara is input from MSB data.
5
5 Page 
PHASE CHARACTERISTICS (∆f vs. DO OUTPUT ENERGY)
150
MB1501
MB1501H
MB1501L
100
50
0
100 80 60 40 20
0
40 60 80
20
–50
–100
–150
MB1501H
MB1501
MB1501L
Time ∆f (ns)
VP
10k
DO
10k
Oscilloscope
VCC=VP=3.0V
fINSfOSC=12MHz
fr=fP=46.9kHz
É(+) Energy
ÉÉÉÉÉÉÉ(–) Energy
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MB1501L.PDF ] | |
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