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부품번호 | MB1502 기능 |
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기능 | SERIAL INPUT PLL FREQUENCY SYNTHESIZER | ||
제조업체 | Fujitsu | ||
로고 | |||
전체 15 페이지수
November 1990
Edition 5.0
DATA SHEET
MB1502
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
LOW POWER SERIAL INPUT PLL SYNTHESIZER
WITH 1.1 GHz PRESCALER
The Fujitsu MB1502, utilizing BI-CMOS technology, is a single chip serial input PLL
synthesizer with pulse-swallow function. The MB1502 contains a 1.1GHz two
modulus prescaler that can select of either 64/65 or 128/129 divide ratio, control
signal generator, 16-bit shift register, 15-bit latch, programmable reference divider
(binary 14-bit programmable reference counter), 1-bit switch counter, phase
comparator with phase conversion function, charge pump, crystal oscillator, 19-bit
shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and
binary 11-bit programmable counter) and analog switch to speed up lock up time.
It operates supply voltage of 5V typ. and achieves very low supply current of 8mA typ.
realized through the use of Fujitsu Advanced Process Technology.
FEATURES
• High operating frequency: fIN MAX=1.1GHz (VIN MIN=10dBm)
• Pulse swallow function: 64/65 or 128/129
• Low supply current: ICC=8mA typ.
• Serial input 18-bit programmable divider consisting of:
— Binary 7-bit swallow counter: 0 to 127
— Binary 11-bit programmable counter: 16 to 2047
• Serial input 15-bit programmable reference divider consisting of:
— Binary 14-bit programmable reference counter: 8 to 16383
— 1-bit switch counter (SW) sets divide ratio of prescaler
• On-chip analog switch achieves fast lock up time
• 2 types of phase detector output
— On-chip charge pump (Bipolar type)
— Output for external charge pump
• Wide operating temperature: –40_C to +85_C
• 16-pin Plastic DIP Package (Suffix: —P)
16-pin Plastic Flat Package (Suffix: —PF)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
RatIng
Symbol
Value
Unit
Power Supply Voltage
Output Voltage
Open-drain Voltage
Output Current
Storage Temperature
VCC
VP
VOUT
VOOP
IOUT
TSTG
–0.5 to +7.0
VCC to 10.0
–0.5 to VCC +0.5
–0.5 to 0.8
± 10
–55 to +125
V
V
V
V
mA
_C
NOTE:
Permanent device damage may occur if the above Absolute Maximum RatIngs are exceed-
ed.Functional operation should be restricted to the condItions as detailed in the operational
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Plastic Package
DIP-16P-M04
Plastic Package
FPT-16P–M06
Pin Assignment
OSCIN
OSCOUT
VP
VCC
DO
GND
LD
fIN
1 16 ∅R
2 15 ∅P
3 14 fOUT
4 13 BiSW
5 (TOP VIEW) 12 FC
6 11 LE
7 10 Data
8 9 Clock
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.
Coypright © 1990 by FUJITSU LIMITED
MB1502
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored
data is transferred into latch depending upon the control bit.
Control data “H” data is transferred into 15-bit latch.
Control data “L” data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.
Control bit
LSB
Divide ratio of prescaler setting bit
MSB
CSSSSSSSSSSSSSSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 W
Divide ratio of programmable reference counter setting bit
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide S S S S S S S S S S S S S S
Ratio
R 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8 00000000001000
9 00000000001001
• ••••••••••••••
16383
11111111111111
NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
SW: This bit selects divide ratio of prescaler.
SW=H : 64
SW=L :128
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown on following page.
4
4페이지 MB1502
fr
fp
LD
H
Do
Z
L
NOTES: Phase difference detection range: –2π to +2π
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.
ANALOG SWITCH
ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) to be
connected to BlSW pin. When the analog switch is OFF, BlSW pin is set to high-impedance state.
LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
LE=L (Normal operating mode): Analog switch=OFF
LPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.
CHARGE PUMP
Do
LPF-1
(CONTROL SIGNAL)
ANALOG SW
BISW
LPF-2
VCO
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input Voltage
Operating Temperature
Symbol
VCC
VP
VI
TA
Min
4.5
VCC
GND
–40
Value
Typ
5.0
VP
Max
5.5
8.0
VCC
85
Unit
V
V
V
_C
7
7페이지 | |||
구 성 | 총 15 페이지수 | ||
다운로드 | [ MB1502.PDF 데이터시트 ] |
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |