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74VHCT74A 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 74VHCT74A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 74VHCT74A 자료 제공

부품번호 74VHCT74A 기능
기능 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
제조업체 STMicroelectronics
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74VHCT74A 데이터시트, 핀배열, 회로
® 74VHCT74A
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
fMAX =160 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHCT74A is an advanced high-speed
CMOS DUAL D-TYPE FLIP FLOP WITH
PRESET AND CLEAR fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology.
A signal on the D INPUT is transfered to the Q
OUTPUT during the positive going transition of
SOP
TSSOP
PACKAGE
SOP
TSSOP
ORDER CODES
T UB E
T&R
74VHCT74AM 74VHCT74AMTR
74VHCT74ATTR
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 2000
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74VHCT74A pdf, 반도체, 판매, 대치품
74VHCT74A
AC ELECTRICAL CHARACTERISTICS (Input tr = tf =3 ns)
Symb ol
Parameter
tPLH Propagation Delay
tPHL Time CK to Q or Q
tPLH Propagation Delay
tPHL Time
PR or CLR to Q or Q
tw CK Pulse Width
HIGH or LOW
tw PR or CLR Pulse
Width LOW
ts Setup Time D to CK
HIGH or LOW
th Hold Time D to CK
HIGH or LOW
tREM Removal Time CLR or
PR to CK
fMAX Maximum Clock
Frequency
(*) Voltage range is 5V ± 0.5V
Test Condition
V CC
( V)
CL
(pF)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
15
50
15
50
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
15
50
Value
TA = 25 oC
Min. Typ. Max.
5.8 7.8
6.3 8.8
7.6 10.4
8.1 11.4
-40 to 85 oC
Min . Max.
1.0 9.0
1.0 10.0
1.0 12.0
1.0 13.0
Unit
ns
ns
5.0 5.0 ns
5.0 5.0 ns
5.0 5.0 ns
0.0 0.0 ns
3.5 3.5 ns
100 160 80 MHz
80 140
65
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
Test Conditions
Value
Un it
TA = 25 oC
-40 to 85 oC
Min. Typ . Max. Min . Max.
CIN Input Capacitance
4 10
10 pF
CPD Power Dissipation
Capacitance (note 1)
10.5 pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/2 (per Gate)
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74VHCT74A 전자부품, 판매, 대치품
WAVEFORM 3: REMOVAL TIMES (f=1MHz; 50% duty cycle)
74VHCT74A
WAVEFORM 4: PULSE WIDTH
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