Datasheet.kr   

M2V28D40ATP-75 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 M2V28D40ATP-75은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 M2V28D40ATP-75 자료 제공

부품번호 M2V28D40ATP-75 기능
기능 128M Double Data Rate Synchronous DRAM
제조업체 Mitsubishi
로고 Mitsubishi 로고


M2V28D40ATP-75 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 30 페이지수

미리보기를 사용할 수 없습니다

M2V28D40ATP-75 데이터시트, 핀배열, 회로
DDR SDRAM (Rev.0.1)
Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S28D20ATP is a 4-bank x 8388608-word x 4-bit,
M2S28D30ATP is a 4-bank x 4194304-word x 8-bit,
M2S28D40ATP is a 4-bank x 2097152-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very
high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- FET switch control(/QFC) for x4/ x8
- JEDEC standard
MITSUBISHI ELECTRIC
1




M2V28D40ATP-75 pdf, 반도체, 판매, 대치품
DDR SDRAM (Rev.0.1)
Jun,'00 Preliminary
PIN FUNCTION
SYMBOL
TYPE
CLK, /CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
BA0,1
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
Input
Input / Output
DQS
Input / Output
/QFC
Output
DM Input
Vdd, Vss
VddQ, VssQ
Vref
Power Supply
Power Supply
Input
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CLK and negative edge of /CLK. Output (read) data is referenced to
the crossings of CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto /
self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to
indicate precharge option. When A10 is high at a read / write
command, an auto precharge is performed. When A10 is high at a
precharge command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
FET Control: Optional. Output during every Read and Write access. Can
be used to control isolation switches on modules. Open drain output.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-
DQ7; UDM corresponds to the data on DQ8-DQ15.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
SSTL_2 reference voltage.
MITSUBISHI ELECTRIC
4

4페이지










M2V28D40ATP-75 전자부품, 판매, 대치품
DDR SDRAM (Rev.0.1)
Jun,'00 Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
Command
IDLE
H X X XX
DESEL
L H H HX
NOP
L H H L BA
TERM
L H L X BA, CA, A10 READ / WRITE
L L H H BA, RA
ACT
L L H L BA, A10
PRE / PREA
L L L HX
REFA
L L L L Op-Code, Mode- MRS
Add
ROW ACTIVE H X X X X
DESEL
L H H HX
NOP
L H H L BA
TERM
L H L H BA, CA, A10 READ / READA
LH
LL
LL
LL
LL
READ(Auto- H X
Precharge L H
Disabled) L H
L L BA, CA, A10 WRITE / WRITEA
H H BA, RA
ACT
H L BA, A10
PRE / PREA
L HX
REFA
L L Op-Code, Mode- MRS
Add
X XX
DESEL
H HX
NOP
H L BA
TERM
L H L H BA, CA, A10 READ / READA
L H L L BA, CA, A10 WRITE / WRITEA
L L H H BA, RA
ACT
L L H L BA, A10
PRE / PREA
L L L HX
REFA
Op-Code, Mode-
L L L L Add
MRS
Action
NOP
NOP
ILLEGAL
ILLEGAL
Bank Active, Latch RA
NOP
Auto-Refresh
Mode Register Set
NOP
NOP
NOP
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Bank Active / ILLEGAL
Precharge / Precharge All
ILLEGAL
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
Terminate Burst, Latch CA, Begin
New Read, Determine Auto-
Precharge
ILLEGAL
Bank Active / ILLEGAL
Terminate Burst, Precharge
ILLEGAL
ILLEGAL
Notes
2
2
4
5
5
2
3
2
MITSUBISHI ELECTRIC
7

7페이지


구       성 총 30 페이지수
다운로드[ M2V28D40ATP-75.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
M2V28D40ATP-75

128M Double Data Rate Synchronous DRAM

Mitsubishi
Mitsubishi

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵