Datasheet.kr   

M2V28S20TP 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 M2V28S20TP은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 M2V28S20TP 자료 제공

부품번호 M2V28S20TP 기능
기능 128M Synchronous DRAM
제조업체 Mitsubishi
로고 Mitsubishi 로고


M2V28S20TP 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

M2V28S20TP 데이터시트, 핀배열, 회로
SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as
4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20TP,M2V28S30TP,M2V28S40TP achieves very high speed data rates up to 133MHz, and is
suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle Time
(Min.)
Active to Precharge Command Period
Row to Column Delay
Access Time from CLK
Ref/Active Command Period
Operation Current
(Max.)
(Single Bank)
Self Refresh Current
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
V28S20
V28S30
V28S40
(Max.)
M2V28S20/30/40TP
-6 -7
-8
7.5ns
10ns 10ns
45ns 50ns
50ns
20ns
5.4ns
67.5ns
20ns
6ns
70ns
20ns
6ns
70ns
120mA 115mA 115mA
130mA
-
120mA
135mA
120mA
135mA
2mA
2mA
2mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- PC133(-6) supports x4/x8 only. And does not support Low-Power (L) version.
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40TP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20TP/30TP/40TP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1




M2V28S20TP pdf, 반도체, 판매, 대치품
SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
4096 x1024 x8
Cell Array
Bank #0
Memory Array
4096 x1024 x8
Cell Array
Bank #1
Memory Array
4096 x1024 x8
Cell Array
Bank #2
Memory Array
4096 x1024 x8
Cell Array
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-11 BA0,1
CLK CKE
/CS /RAS
/CAS
/WE
Note : This figure shows the M2V28S30TP.
The M2V28S20TP configration is 4096x2048x4 of cell array and DQ 0-3.
The M2V28S40TP configration is 4096x512x16 of cell array and DQ 0-15.
DQM
Type Designation Code
M2 V 28 S 3 0
TP -8
These rules are only applied to the Synchronous DRAM family.
Access Item
Package Type
Process Generation
Function
Organization
Synchronous DRAM
Density
Interface
Mitsubishi DRAM
-6 : 7.5ns (PC133/3-3-3),
-7 : 10ns(PC100/2-2-2),
-8 : 10ns(PC100/3-2-2)
TP : TSOP(II)
Blank : 1st gen.
0 : Random Column
2: x4, 3: x8, 4: x16
28 : 128Mbit
V : LVTTL
MITSUBISHI ELECTRIC
4

4페이지










M2V28S20TP 전자부품, 판매, 대치품
SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
COMMAND TRUTH TABLE
COMMAND
MNEMONIC CKE CKE /CS /RAS /CAS /WE BA0,1 A11 A10 A0-9
n-1 n
Deselect
DESEL
HX HXXX X X XX
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
NOP
ACT
PRE
H X L HHH X X X X
H X L L HH V V V V
HX L LHL VX LX
Precharge All Banks
Column Address Entry
& Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
PREA
WRITE
WRITEA
READ
READA
REFA
HX L L HL X XHX
HXLHLL VVLV
HX LHL L V VHV
HX L HLH V V L V
HX LHLH V VHV
HHLL LHXXXX
Self-Refresh Entry
REFS
HL LL LHXXXX
Self-Refresh Exit
REFSX
L HHXXX X X XX
L H L HHH X X X X
Mode Register Set
MRS
H X L L L L L L L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
7

7페이지


구       성 총 30 페이지수
다운로드[ M2V28S20TP.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
M2V28S20TP

128M Synchronous DRAM

Mitsubishi
Mitsubishi

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵