M2V56D30AKT-75A Datasheet PDF - Mitsubishi
| Part Number | M2V56D30AKT-75A | |
| Description | 256M Double Data Rate Synchronous DRAM | |
| Manufacturers | Mitsubishi | |
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DDR SDRAM
(Rev.1.44)
Mar. '02
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
Contents are subject to change without notice.
DESCRIPTION
M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit,
M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit,
M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieve very high
speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- VDD=VDDQ=2.5V+0.2V
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
- Commands are entered on each positive CLK edge
- Data and data mask are referenced to both edges of DQS
- 4-bank operations are controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge is controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- Both 66-pin TSOP Package and 64-pin Small TSOP Package
M2S56D*0ATP: 0.8mm lead pitch 66-pin TSOP Package
M2S56D*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package
- JEDEC standard
- Low Power for the Self Refresh Current ICC6 : 2mA (-75AL , -75L , -10L)
Operating Frequencies
Max. Frequency Max. Frequency
@CL=2.0 *
@CL=2.5 *
M2S56D20/30/40ATP/AKT-75AL/-75A
133MHz
133MHz
Standard
DDR266A
M2S56D20/30/40ATP/AKT-75L/-75
100MHz
133MHz
DDR266B
M2S56D20/30/40ATP/AKT-10L/-10
100MHz
* CL = CAS(Read) Latency
125MHz
DDR200
MITSUBISHI ELECTRIC
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DDR SDRAM
(Rev.1.44)
Mar. '02
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
CLK, /CLK
TYPE
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-12
Input
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh.After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
DQS
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Input / Output Data Input/Output: Data bus
Input / Output
Data Strobe: Output pin during Read operation, input pin during Write
operation. Edge-aligned with read data, placed at the centered of write data
to capture the write data. For the x16, LDQS corresponds to the data on
DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with the input data
DM
Input
during a WRITE operations. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
VDD, VSS Power Supply Power Supply for the memory array and peripheral circuitry.
VDDQ, VSSQ Power Supply VDDQ and VSSQ are supplied to the Output Buffers only.
VREF
Input
SSTL_2 reference voltage.
MITSUBISHI ELECTRIC
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for M2V56D30AKT-75A electronic component. |
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