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부품번호 | M2V56D30ATP75A 기능 |
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기능 | 256M Double Data Rate Synchronous DRAM | ||
제조업체 | Mitsubishi | ||
로고 | |||
DDR SDRAM (Rev.1.2)
Jun. '01 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit,
M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit,
M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40ATP achieves very
high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
Operating Frequencies
Speed
Grade
-75A
-75
-10
Clock Rate
CL=2 *
133MHz
CL=2.5 *
133MHz
100MHz 133MHz
100MHz 125MHz
* CL = CAS(Read) Latency
MITSUBISHI ELECTRIC
1
DDR SDRAM (Rev.1.2)
Jun. '01 Preliminary
BLOCK DIAGRAM
DLL
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
DQ0 - 15
UDQS,LDQS
I/O Buffer
QS Buffer
Memory
Array
Bank #0
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Address Buffer
A0-12 BA0,1
Control Circuitry
Clock Buffer
Control Signal Buffer
/CS /RAS /CAS /WE UDM,
CLK /CLK CKE
LDM
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 2 S 56 D 3 0 A TP –75A
Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0
75: 133MHz@CL=2.5,100MHz@CL=2.0
75A: 133MHz@CL=2.5,133MHz@CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2 n 2: x4, 3: x8, 4: x16
DDR Synchronous DRAM
Density 56: 256M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
4
4페이지 DDR SDRAM (Rev.1.2)
Jun. '01 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30/ 40ATP
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
Command
IDLE
H X X XX
DESEL
L H H HX
NOP
L H H L BA
TERM
L H L X BA, CA, A10 READ / WRITE
L L H H BA, RA
ACT
L L H L BA, A10
PRE / PREA
L L L HX
REFA
LL
L L Op-Code, Mode- MRS
Add
ROW ACTIVE H X X X X
DESEL
L H H HX
NOP
L H H L BA
TERM
L H L H BA, CA, A10 READ / READA
L
L
L
L
L
READ(Auto-
Precharge
Disabled)
H
L
L
H
L
L
L
L
X
H
H
L L BA, CA, A10 WRITE / WRITEA
H H BA, RA
ACT
H L BA, A10
PRE / PREA
L HX
REFA
L L Op-Code, Mode- MRS
Add
X XX
DESEL
H HX
NOP
H L BA
TERM
L H L H BA, CA, A10 READ / READA
LH
LL
LL
LL
LL
L L BA, CA, A10 WRITE / WRITEA
H H BA, RA
ACT
H L BA, A10
PRE / PREA
L HX
REFA
Op-Code, Mode-
L L Add
MRS
Action
NOP
NOP
ILLEGAL
ILLEGAL
Bank Active, Latch RA
NOP
Auto-Refresh
Mode Register Set
NOP
NOP
NOP
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Bank Active / ILLEGAL
Precharge / Precharge All
ILLEGAL
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
Terminate Burst, Latch CA, Begin
New Read, Determine Auto-
Precharge
ILLEGAL
Bank Active / ILLEGAL
Terminate Burst, Precharge
ILLEGAL
ILLEGAL
Notes
2
2
4
5
5
2
3
2
MITSUBISHI ELECTRIC
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
M2V56D30ATP75A | 256M Double Data Rate Synchronous DRAM | Mitsubishi |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |