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M2V56D30TP-75 데이터시트 PDF




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부품번호 M2V56D30TP-75 기능
기능 256M Double Data Rate Synchronous DRAM
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M2V56D30TP-75 데이터시트, 핀배열, 회로
DDR SDRAM (Rev.0.0)
Sep.'99 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S56D20TP is a 4-bank x 16777216-word x 4-bit,
M2S56D30TP is a 4-bank x 8388608-word x 8-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30 TP achieves very high
speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5v±0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 1.5/2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- FET switch control(/QFC)
- JEDEC standard
PIN CONFIGURATION
(TOP VIEW)
x8
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU/QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6
7
66pin TSOP(II)
61
60
8 59
9 58
10 57
11 56
12
13
400mil width
55
54
14 x 53
15 875mil length 52
16 51
17 50
18 49
19
20
21
0.65mm
Lead Pitch
48
47
46
22 45
23 44
24
25
ROW
43
42
26 A0-12
41
27
28
29
Column
A0-9,11(x4)
40
39
38
30 A0-9 (x8) 37
31 36
32 35
33 34
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
MITSUBISHI
ELECTRIC
1




M2V56D30TP-75 pdf, 반도체, 판매, 대치품
DDR SDRAM (Rev.0.0)
Sep.'99 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
CLK,/CLK
CKE
TYPE
Input
Input
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
A0-12
BA0,1
DQ0-7(x8),
DQ0-3(x4)
DQS
/QFC
DM
Vdd, Vss
Input
Input
Input
Input / Output
Input / Output
Output
Input
Power Supply
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-12. The Column Address is specified by
A0-9,11(x4) and A0-9(x8). A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
FET Control: Optional. Output during every Read and Write access. Can
be used to control
isolation switches on modules. Open drain output.
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM pins
are input only, the DM loading matches the DQ and DQS loading.
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Vref
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Input
SSTL_2 reference voltage.
MITSUBISHI
ELECTRIC
4

4페이지










M2V56D30TP-75 전자부품, 판매, 대치품
DDR SDRAM (Rev.0.0)
Sep.'99 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
IDLE
H X X XX
L H H HX
L H H L BA
L H L X BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
ROW ACTIVE H X X X X
L H H HX
L H H L BA
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
READ
H X X XX
(Auto-
L H H HX
Precharge
Disabled)
L H H L BA
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
Command
Action
DESEL NOP
NOP
NOP
TERM
ILLEGAL
READ / WRITE ILLEGAL
ACT
Bank Active, Latch RA
PRE / PREA NOP
REFA
Auto-Refresh
MRS
Mode Register Set
Notes
2
2
4
5
5
DESEL NOP
NOP
NOP
TERM
NOP
Begin Read, Latch CA,
READ / READA
Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
ACT
Bank Active / ILLEGAL
PRE / PREA Precharge / Precharge All
REFA
ILLEGAL
2
MRS
ILLEGAL
DESEL NOP (Continue Burst to END)
NOP
NOP (Continue Burst to END)
TERM
Terminate Burst
Terminate Burst, Latch CA,
READ / READA Begin New Read, Determine
Auto-Precharge
WRITE
WRITEA
ILLEGAL
ACT
Bank Active / ILLEGAL
PRE / PREA Terminate Burst, Precharge
REFA
ILLEGAL
3
2
MRS
ILLEGAL
MITSUBISHI
ELECTRIC
7

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부품번호상세설명 및 기능제조사
M2V56D30TP-75

256M Double Data Rate Synchronous DRAM

Mitsubishi
Mitsubishi

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