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M2V56S20AKT 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 M2V56S20AKT은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 M2V56S20AKT 기능
기능 256M Synchronous DRAM
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M2V56S20AKT 데이터시트, 핀배열, 회로
SDRAM (Rev.1.01)
Single Data Rate
July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20AKT is a 4-bank x 16777216-word x 4-bit,
M2V56S30AKT is a 4-bank x 8388608-word x 8-bit,
M2V56S40AKT is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- Single Data Rate
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/full page (programmable)
- Burst type- sequential / interleave (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- LVTTL Interface
- 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch
M2V56S20/30/40 AKT -5
Max. Frequency
@CL2
133 MHz
M2V56S20/30/40 AKT -6
100MHz
M2V56S20/30/40 AKT -7
100 MHz
Max. Frequency
@CL3
166 MHz
133 MHz
100MHz
Standard
PC133 (CL2)
PC133 (CL3)
PC100 (CL2)
MITSUBISHI ELECTRIC
1




M2V56S20AKT pdf, 반도체, 판매, 대치품
SDRAM (Rev.1.01)
Single Data Rate
July '01
PIN FUNCTION
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto
/ self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12
BA0,1
Input
Input
A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12. The Column Address is
specified by A0-9,11. A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.
Bank Address: BA0,1 specifies one of four banks to which a command
is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
commands.
DQ0-15
Input / Output Data In and Data out are referenced to the rising edge of CLK.
DQM
DQMU/L
Input
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for
the current cycle is masked. When DQMU/L is high in burst read, Dout
is disabled at the next but one cycle.
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
MITSUBISHI ELECTRIC
4

4페이지










M2V56S20AKT 전자부품, 판매, 대치품
SDRAM (Rev.1.01)
Single Data Rate
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
July '01
256M Synchronous DRAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE
Address
Command
Action
IDLE
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H LX
TBST
ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA
ACT
Bank Active, Latch RA
L L H L BA, A10
PRE / PREA NOP*4
L L L HX
Op-Code,
L L L L Mode-Add
REFA
MRS
Auto-Refresh*5
Mode Register Set*5
ROW ACTIVE H X X X X
DESEL NOP
L H H HX
NOP
NOP
L H H LX
TBST
NOP
Begin Read, Latch CA,
L H L H BA, CA, A10 READ / READA
Determine Auto-Precharge
WRITE / Begin Write, Latch CA,
L H L L BA, CA, A10
WRITEA Determine Auto-Precharge
L L H H BA, RA
ACT
Bank Active / ILLEGAL*2
L L H L BA, A10
PRE / PREA Precharge / Precharge All
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
READ
H X X XX
DESEL NOP (Continue Burst to END)
L H H HX
NOP
NOP (Continue Burst to END)
L H H LX
TBST
Terminate Burst
Terminate Burst, Latch CA,
L H L H BA, CA, A10 READ / READA Begin New Read, Determine
Auto-Precharge*3
Terminate Burst, Latch CA,
WRITE /
L H L L BA, CA, A10
Begin Write, Determine Auto-
WRITEA
Precharge*3
L L H H BA, RA
ACT
Bank Active / ILLEGAL*2
L L H L BA, A10
PRE / PREA Terminate Burst, Precharge
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MITSUBISHI ELECTRIC
7

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부품번호상세설명 및 기능제조사
M2V56S20AKT

256M Synchronous DRAM

Mitsubishi
Mitsubishi

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