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M2V64S20BTP-6 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 M2V64S20BTP-6은 전자 산업 및 응용 분야에서
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부품번호 M2V64S20BTP-6 기능
기능 64M bit Synchronous DRAM
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M2V64S20BTP-6 데이터시트, 핀배열, 회로
PC133 SDRAM (Rev.0.5)
Oct. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized
as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit
Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. M2V64S20BTP,M2V64S30BTP,M2V64S40BTP achieves very high speed data rates up to
133MHz, and is suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK Clock Cycle Time
(Min.)
tRAS Active to Precharge Command Period
(Min.)
tRCD Row to Column Delay
(Min.)
tAC Access Time from CLK
(Max.) (CL=3)
tRC Ref/Active Command Period
Icc1 Operation Current (Max.) [Single Bank]
(Min.)
Icc6 Self Refresh Current
(Max.)
M2V64S20TP
M2V64S30TP
M2V64S40TP
-6
7.5ns
45ns
20.0ns
5.4ns
67.5ns
120mA
1mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6 : 133MHz [PC133<3-3-3> ]
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1




M2V64S20BTP-6 pdf, 반도체, 판매, 대치품
PC133 SDRAM (Rev.0.5)
Oct. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is ceased. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-11. The Column Address is specified by
A0-A9(x4), A0-A8(x8), A0-7(x16) . A10 is also used to indicate precharge
option. When A10 is high at a read / write command, an auto precharge
is performed. When A10 is high at a precharge command, all banks are
precharged.
BA0,1
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
DQM(x4,x8),
DQMU/L(x16)
Input
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Input / Output Data In and Data out are referenced to the rising edge of CLK.
Input
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the
current cycle is masked. When DQMU/L is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only.
MITSUBISHI ELECTRIC
4

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M2V64S20BTP-6 전자부품, 판매, 대치품
PC133 SDRAM (Rev.0.5)
Oct. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address
IDLE
H X X XX
L H H HX
L H H L BA
L H L X BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
ROW ACTIVE H X X X X
L H H HX
L H H L BA
L H L H BA, CA, A10
READ
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
H X X XX
L H H HX
L H H L BA
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
Command
Action
DESEL
NOP
NOP
NOP
TBST
ILLEGAL*2
READ / WRITE ILLEGAL*2
ACT
Bank Active, Latch RA
PRE / PREA NOP*4
REFA
Auto-Refresh*5
MRS
Mode Register Set*5
DESEL
NOP
NOP
NOP
TBST
NOP
Begin Read, Latch CA,
READ / READA
Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
ACT
Bank Active / ILLEGAL*2
PRE / PREA Precharge / Precharge All
REFA
ILLEGAL
MRS
ILLEGAL
DESEL
NOP (Continue Burst to END)
NOP
NOP (Continue Burst to END)
TBST
Terminate Burst
Terminate Burst, Latch CA,
READ / READA Begin New Read, Determine
Auto-Precharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
ACT
Bank Active / ILLEGAL*2
PRE / PREA Terminate Burst, Precharge
REFA
ILLEGAL
MRS
ILLEGAL
MITSUBISHI ELECTRIC
7

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