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PDF M2V64S30DTP-7 Data sheet ( Hoja de datos )
| Número de pieza | M2V64S30DTP-7 | |
| Descripción | 64M Synchronous DRAM | |
| Fabricantes | Mitsubishi | |
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MITSUBISHI LSIs
SDRAM (Rev.3.2)
Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 8-BIT)
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
PRELIMINARY
Some of contents are described for general products and are
subject to change w ithout notice.
DESCRIPTION
M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,
M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,
M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,
synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up
to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
Clock Cycle T ime
Active to Precharge Command Period
Row to Column Delay
(Min.)
(Min.)
(Min.)
tAC Access Time from CLK
(Max.) (CL=3)
tRC Ref /Active Command Period
(Min.)
Icc1 Operation Current
(Max.)
(Single Bank)
V64S20D
V64S30D
V64S40D
Icc6 Self Refresh Current
(Max.)
M2V64S20/30/40DTP
-6 -7
-8
7.5ns
45ns
20ns
10ns
50ns
20ns
10ns
50ns
20ns
5.4ns
67.5ns
6ns
70ns
6ns
70ns
75mA 70mA
70mA
75mA 70mA
70mA
85mA 80mA
80mA
1mA
1mA
1mA
- Single 3.3v±0.3V power supply
- Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQM L and DQMU for M2V64S40DTP
- Random column access
- Auto p recharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1
1 page  
MITSUBISHI LSIs
SDRAM (Rev.3.2)
Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 8-BIT)
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
BASIC FUNCTIONS
The M 2V64S20, 30 and 40DTP provides basic functions, bank (row) activate, burst read and write, bank
(row) precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option,
and precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command def ine basic commands
Command
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
p recharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-p recharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
5 Page 
MITSUBISHI LSIs
SDRAM (Rev.3.2)
Feb.'00
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 2,097,152-WORD x 8-BIT)
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE Address
Command Action
WRIT E
H X X XX
RECOVERING
L H H HX
DESEL NOP
NOP NOP
L H H LX
TBST ILLEGAL*2
L H L X BA, CA, A10 READ & ILLEGAL*2
WRIT E
L L H H BA, RA
ACT ILLEGAL*2
L L H L BA, A10
PRE & ILLEGAL*2
PREA
L L L HX
Op-Code,
L L LL
Mode-Add
REFA ILLEGAL
MRS ILLEGAL
REFRESHING H X X X X
DESEL NOP (Idle after tRC)
L H H HX
NOP NOP (Idle after tRC)
L H H LX
TBST ILLEGAL
READ &
L H L X BA, CA, A10
ILLEGAL
WRIT E
L L H H BA, RA
ACT ILLEGAL
L L H L BA, A10
PRE &
ILLEGAL
PREA
L L L HX
Op-Code,
L L LL
Mode-Add
REFA ILLEGAL
MRS ILLEGAL
MITSUBISHI ELECTRIC
11
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