M68Z128-55N1 Datasheet PDF - ST Microelectronics
| Part Number | M68Z128-55N1 | |
| Description | 5V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable | |
| Manufacturers | ST Microelectronics | |
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There is a preview and M68Z128-55N1 download ( pdf file ) link at the bottom of this page. Total 12 Pages | ||
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M68Z128
5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
s ULTRA LOW DATA RETENTION CURRENT
– 10nA (typical)
– 2.0µA (max)
s OPERATION VOLTAGE: 5V ±10%
s 128Kb x 8 VERY FAST SRAM with OUTPUT
ENABLE
s EQUAL CYCLE and ACCESS TIMES: 55ns
s LOW VCC DATA RETENTION: 2V
s TRI-STATE COMMON I/O
s LOW ACTIVE and STANDBY POWER
s AUTOMATIC POWER-DOWN WHEN
DESELECTED
s INTENDED FOR USE WITH ST
ZEROPOWER® AND TIMEKEEPER®
CONTROLLERS
DESCRIPTION
The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS
SRAM, organized as 131,072 words by 8 bits. The
device features fully static operation requiring no
external clocks or timing strobes, with equal ad-
dress access and cycle times. It requires a single
5V ±10% supply, and all inputs and outputs are
TTL compatible.
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Input/Output
E1 Chip Enable 1
E2 Chip Enable 2
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
VCC
17
A0-A16
8
DQ0-DQ7
W
M68Z128
E1
E2
G
VSS
AI00647
March 2000
1/12
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M68Z128
Table 7. Read and Standby Modes AC Characteristics
(TA = 0 to 70°C; VCC = 5V ±10%)
M68Z128
Symbol
Parameter
-55 Unit
Min Max
tAVAV Read Cycle Time
55 ns
tAVQV (1) Address Valid to Output Valid
55 ns
tE1LQV (1) Chip Enable 1 Low to Output Valid
55 ns
tE2HQV (1) Chip Enable 2 High to Output Valid
55 ns
tGLQV (1) Output Enable Low to Output Valid
20 ns
tE1LQX (3) Chip Enable 1 Low to Output Transition
5 ns
tE2HQX (3) Chip Enable 2 High to Output Transition
5 ns
tGLQX (3) Output Enable Low to Output Transition
0 ns
tE1HQZ (2,3) Chip Enable 1 High to Output Hi-Z
20 ns
tE2LQZ (2,3) Chip Enable 2 Low to Output Hi-Z
20 ns
tGHQZ (2,3) Output Enable High to Output Hi-Z
20 ns
tAXQX (1) Address Transition to Output Transition
5 ns
tPU Chip Enable 1 Low or Chip Enable 2 High to Power Up
0
ns
tPD Chip Enable 1 High or Chip Enable 2 Low to Power Down
55 ns
Note: 1. CL = 100pF.
2. CL = 5pF.
3. At any given temperature and voltage condition, tEIHQZ + tEZHQZ is less than tEILQX and tEZLQX, tGHQZ is less than tGLQX for any
given device.
Figure 5. Address Controlled, Read Mode AC Waveforms
A0-A16
DQ0-DQ7
tAVQV
tAVAV
VALID
DATA VALID
tAXQX
AI01078
Note: E1 = Low, E2 = High, G = Low, W = High.
5/12
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for M68Z128-55N1 electronic component. |
| Information | Total 12 Pages | |
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| Download | [ M68Z128-55N1.PDF Datasheet ] | |
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