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PDF M68Z128WN Data sheet ( Hoja de datos )
| Número de pieza | M68Z128WN | |
| Descripción | 3V / 1 Mbit 128Kb x8 Low Power SRAM with Output Enable | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M68Z128W
3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
s LOW VOLTAGE: 3.0V (+0.6V / –0.3V)
s 128Kb x 8 LOW POWER SRAM with OUTPUT
ENABLE
s EQUAL CYCLE and ACCESS TIMES: 70ns
s LOW VCC DATA RETENTION: 1.4V
s TRI-STATE COMMON I/O
s LOW ACTIVE and STANDBY POWER
s INTENDED for USE with ST ZEROPOWER®
and TIMEKEEPER® CONTROLLERS
DESCRIPTION
The M68Z128W is a 1 Mbit (1,048,576 bit) Fast
CMOS SRAM, organized as 131,072 words by 8
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 3.0V (+0.6V / –0.3V) supply, and all inputs
and outputs are TTL compatible. This device has
an automatic power-down feature, reducing the
power consumption by over 99% when deselect-
ed. The M68Z128W is available in the standard
450mil-wide TSOP type 1 package.
TSOP32 (N)
8 x 20mm
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Input/Output
E1 Chip Enable 1
E2 Chip Enable 2
G Output Enable
W Write Enable
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
17
A0-A16
8
DQ0-DQ7
W
M68Z128W
E1
E2
G
VSS
AI01878B
March 2000
1/12
1 page  
M68Z128W
Table 7. Read and Standby Modes AC Characteristics
(TA = 0 to 70°C; VCC = 3.0V + 0.6V / –0.3V)
M68Z128W
Symbol
Parameter
-70 Unit
Min Max
tAVAV Read Cycle Time
70 ns
tAVQV (1) Address Valid to Output Valid
70 ns
tE1LQV (1) Chip Enable 1 Low to Output Valid
70 ns
tE2HQV (1) Chip Enable 2 High to Output Valid
70 ns
tGLQV (1) Output Enable Low to Output Valid
35 ns
tE1LQX (3) Chip Enable 1 Low to Output Transition
10 ns
tE2HQX (3) Chip Enable 2 High to Output Transition
10 ns
tGLQX (3) Output Enable Low to Output Transition
10 ns
tE1HQZ (2,3) Chip Enable 1 High to Output Hi-Z
0 25 ns
tE2LQZ (2,3) Chip Enable 2 Low to Output Hi-Z
0 25 ns
tGHQZ (2,3) Output Enable High to Output Hi-Z
0 25 ns
tAXQX (1) Address Transition to Output Transition
10 ns
tPU Chip Enable 1 Low or Chip Enable 2 High to Power Up
0
ns
tPD Chip Enable 1 High or Chip Enable 2 Low to Power Down
70 ns
Note: 1. CL = 50pF (see Figure 3).
2. CL = 5pF (see Figure 3).
3. At any given temperature and voltage condition, tEIHQZ + tEZHQZ is less than tEILQX and tEZLQX, tGHQZ is less than tGLQX for any
given device.
Figure 5. Address Controlled, Read Mode AC Waveforms
A0-A16
DQ0-DQ7
tAVQV
tAVAV
VALID
DATA VALID
tAXQX
AI01078
Note: E1 = Low, E2 = High, G = Low, W = High.
5/12
5 Page 
M68Z128W
Table 12. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
mm inch
Symbol
Typ Min Max Typ Min Max
A
1.200
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
B
0.150
0.270
0.0059
0.0106
C
0.100
0.210
0.0039
0.0083
D
19.800
20.200
0.7795
0.7953
D1
18.300
18.500
0.7205
0.7283
e 0.500 –
– 0.0197 –
–
E
7.900
8.100
0.3110
0.3189
L
0.500
0.700
0.0197
0.0276
α 0° 5° 0° 5°
CP
0.100
0.0039
N 32
32
Figure 11. TSOP32 (Type I) - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1N
e
N/2
D1
D
E
B
A
CP
DIE
TSOP-a
Drawing is not to scale.
C
A1 α L
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M68Z128WN.PDF ] | |
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