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M6MGT160S2BVP 데이터시트 PDF




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부품번호 M6MGT160S2BVP 기능
기능 CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-MCP
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M6MGT160S2BVP 데이터시트, 핀배열, 회로
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
DESCRIPTION
FEATURES
The MITSUBISHI M6MGB/T160S2BVP is a Stacked Multi • Access time
Chip Package (S-MCP) that contents 16M-bits flash memory
and 2M-bits Static RAM in a 48-pin TSOP (TYPE-I).
Flash Memory
SRAM
90ns (Max.)
85ns (Max.)
• Supply voltage
Vcc=2.7 ~ 3.6V
16M-bits Flash memory is a 2097152 bytes /1048576 words,
3.3V-only, and high performance non-volatile memory
fabricated by CMOS technology for the peripheral circuit
and DINOR(DIvided bit-line NOR) architecture for the
Ambient temperature
W version
Package : 48-pin TSOP (Type-I)
,
Ta=-20 ~ 85°C
0.4mm lead pitch
memory cell.
2M-bits SRAM is a 262144 bytes / 131072 words
unsynchronous SRAM fabricated by silicon-gate CMOS
APPLICATION
technology.
Mobile communication products
M6MGB/T160S2BVP is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight .
A15
A14
A13
A12
A11
A10
A9
A8
A19
S-CE
WE#
F-RP#
F-WP#
S-VCC
F-RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
F-VCC
S-VCC
GND
A-1-A16
A17-A19
DQ0-DQ15
F-CE#
S-CE
OE#
WE#
F-WP#
F-RP#
F-RY/BY#
BYTE#
48 A16
47 BYTE#
46 GND
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 F-VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 GND
26 F-CE#
25 A0
14.0 mm
:Vcc for Flash
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready /Busy
:Flash/SRAM Byte Enable
NC:Non Connection
1 Sep. 1999 , Rev.2.0




M6MGT160S2BVP pdf, 반도체, 판매, 대치품
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
FUNCTION
The Flash Memory of M6MGB/T160S2BVP includes on-chip
program/erase control circuitry. The Write State Machine (WSM)
controls block erase and byte/page program operations.
Operational modes are selected by the commands written to the
Command User Interface (CUI). The Status Register indicates the
status of the WSM and when the WSM successfully completes the
desired program or block erase operation.
A Deep Powerdown mode is enabled when the F-RP# pin is at
GND, minimizing power consumption.
Deep Power-Down
When F-RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, F-RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
Read
The Flash Memory of M6MGB/T160S2BVP has three read modes,
which accesses to the memory array, the Device Identifier and the
Status Register. The appropriate read command are required to
be written to the CUI. Upon initial device powerup or after exit
from deep powerdown, the Flash Memory automatically resets to
read array mode. In the read array mode, low level input to F-CE#
and OE#, high level input to WE# and F-RP#, and address signals
to the address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode)
output the data of the addressed location to the data input/output
(D7-D0:Byte Mode, D15-D0:Word Mode).
Automatic Power-Saving (APS)
The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or F-CE# isn't
changed more than 200ns after the last alternation. The
power consumption becomes the same as the stand-by
mode. While in this mode, the output data is latched and can
be read out. New data is read out correctly when addresses
are changed.
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing WE# to low level, while F-CE# is at low level and OE# is
at high level. Address and data are latched on the earlier rising
edge of WE# and F-CE#. Standard micro-processor write timings
are used.
Alternating Background Operation (BGO)
The Flash Memory of M6MGB/T160S2BVP allows to read array
from one bank while the other bank operates in software
command write cycling or the erasing / programming operation in
the background. Read array operation with the other bank in BGO
is performed by changing the bank address without any additional
command. When the bank address points the bank in software
command write cycling or the erasing / programming operation,
the data is read out from the status register. The access time with
BGO is the same as the normal read operation.
Output Disable
When OE# is at VIH, output from the devices is disabled. Data
input/output are in a high-impedance(High-Z) state.
Standby
When F-CE# is at VIH, the device is in the standby mode and
its power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
4 Sep. 1999 , Rev.2.0

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M6MGT160S2BVP 전자부품, 판매, 대치품
MITSUBISHI LSIs
M6MGB/T160S2BVP
16,777,216-BIT (1,048,576 -WORD BY 16-BIT / 2,097,152-WORD BY 8-BIT) CMOS
3.3V-ONLY FLASH MEMORY &
2,097,152-BIT (131,072-WORD BY 16-BIT / 262,144-WORD BY 8-BIT) CMOS SRAM
Stacked-MCP (Multi Chip Package)
BUS OPERATIONS
Bus Operations for Word-Wide Mode
Mode
Pins
Array
Read
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
Program
Write
Erase
Others
Deep Power Down
F-CE#
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
OE#
VIL
VIL
VIL
VIL
VIH
X 2)
VIH
VIH
VIH
X
WE#
VIH
VIH
VIH
VIH
VIH
X
VIL
VIL
VIL
X
F-RP#
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
DQ0-15
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
Hi-Z
Command/Data in
Command
Command
Hi-Z
F-RY/BY#
VOH (Hi-Z)
X 1)
X
VOH (Hi-Z)
X
X
X
X
X
VOH (Hi-Z)
Bus Operations for Byte-Wide Mode
Mode
Pins
Array
Read
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
Program
Write
Erase
Others
Deep Power Down
F-CE#
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
OE#
VIL
VIL
VIL
VIL
VIH
X 2)
VIH
VIH
VIH
X
WE#
VIH
VIH
VIH
VIH
VIH
X
VIL
VIL
VIL
X
F-RP#
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
DQ0-7
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
Hi-Z
Command/Data in
Command
Command
Hi-Z
F-RY/BY#
VOH (Hi-Z)
X 1)
X
VOH (Hi-Z)
X
X
X
X
X
VOH (Hi-Z)
1) X at F-RY/BY# is VOL or VOH(Hi-Z).
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition.
2) X can be VIH or VIL for control pins.
7 Sep. 1999 , Rev.2.0

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부품번호상세설명 및 기능제조사
M6MGT160S2BVP

CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-MCP

Mitsubishi
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