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M6MGT166S4BWG 데이터시트 PDF




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부품번호 M6MGT166S4BWG 기능
기능 CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-CSP
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M6MGT166S4BWG 데이터시트, 핀배열, 회로
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
DESCRIPTION
The MITSUBISHI M6MGB/T166S4BWG is a Stacked Chip
Scale Package (S-CSP) that contents 16M-bits flash
memory and 4M-bits Static RAM in a 72-pin S-CSP.
16M-bits Flash memory is a 1,048,576 words, 3.3V-only,
and high performance non-volatile memory fabricated by
CMOS technology for the peripheral circuit and
DINOR(DIvided bit-line NOR) architecture for the memory
cell.
4M-bits SRAM is a 262,144words unsynchronous SRAM
fabricated by silicon-gate CMOS technology.
M6MGB/T166S4BWG is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight .
FEATURES
• Access time
Flash Memory
90ns (Max.)
SRAM
85ns (Max.)
• Supply voltage
Vcc=2.7 ~ 3.6V
• Ambient temperature
W version
Ta=-20 ~ 85°C
• Package : 72-pin S-CSP , 0.8mm ball pitch
APPLICATION
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
HGF E DCB A
NC NC 1
NC NC 2
DU F-A18 S-LB# F-WP# GND F-WE# A16 DU 3
F-
A5 F-A17 S-UB# DU F-RP# RY/BY# A8 A11 4
A4 A7 S-OE# F-A19 DU DU A10 A15 5
A0 A6 DU DQ11 DU S-A17 A9 A14 6
F-CE# A3 DQ9 DU DQ12 DQ13 DQ15 A13 7
F-GND A2
DQ8
DQ10
S-
CE2
DQ6 S-WE# A12 8
F-OE# A1 DQ0 DQ2 S-VCC DQ4 DQ14 9F-GND
DU
S-
CE1#
DQ1 DQ3 F-VCC DQ5 DQ7
DU 10
NC NC 11
NC NC 12
8.0 mm
INDEX
F-VCC
:Vcc for Flash
S-VCC
:Vcc for SRAM
F-GND
:GND for Flash
GND
:Flash/SRAM common GND
A0-A16
:Flash/SRAM
common Address
F-A17-F-A19 :Address for Flash
S-A17
:Address for SRAM
DQ0-DQ15 :Flash/SRAM
common Data I/O
F-CE#
:Flash Chip Enable
S-CE1#
:SRAM Chip Enable
S-CE2
:SRAM Chip Enable
F-OE#
S-OE#
:Flash Output Enable
:SRAM Output Enable
F-WE#
:Flash Write Enable
S-WE#
:SRAM Write Enable
F-WP#
:Flash Write Protect
F-RP#
:Flash Reset Power Down
F-RY/BY# :Flash Ready /Busy
S-LB#
:SRAM Lower Byte
S-UB#
:SRAM Upper Byte
NC:Non Connection
DU:Don't Use (Note: Should be open)
1 Apr. 1999 , Rev.1.7




M6MGT166S4BWG pdf, 반도체, 판매, 대치품
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
FUNCTION
The Flash Memory of M6MGB/T166S4BWG includes on-chip
program/erase control circuitry. The Write State Machine (WSM)
controls block erase and byte/page program operations.
Operational modes are selected by the commands written to the
Command User Interface (CUI). The Status Register indicates the
status of the WSM and when the WSM successfully completes the
desired program or block erase operation.
A Deep Powerdown mode is enabled when the F-RP# pin is at
GND, minimizing power consumption.
Read
The Flash Memory of M6MGB/T166S4BWG has three read
modes, which accesses to the memory array, the Device Identifier
and the Status Register. The appropriate read command are
required to be written to the CUI. Upon initial device powerup or
after exit from deep powerdown, the Flash Memory automatically
resets to read array mode. In the read array mode, low level input
to F-CE# and F-OE#, high level input to F-WE# and F-RP#, and
address signals to the address inputs (F-A19-F-A17,A16-A0)
output the data of the addressed location to the data input/output (
D15-D0).
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing F-WE# to low level, while F-CE# is at low level and F-OE#
is at high level. Address and data are latched on the earlier rising
edge of F-WE# and F-CE#. Standard micro-processor write
timings are used.
Alternating Background Operation (BGO)
The Flash Memory of M6MGB/T166S4BWG allows to read array
from one bank while the other bank operates in software
command write cycling or the erasing / programming operation in
the background. Read array operation with the other bank in BGO
is performed by changing the bank address without any additional
command. When the bank address points the bank in software
command write cycling or the erasing / programming operation,
the data is read out from the status register. The access time with
BGO is the same as the normal read operation.
Output Disable
When F-OE# is at VIH, output from the devices is disabled. Data
input/output are in a high-impedance(High-Z) state.
Standby
When F-CE# is at VIH, the device is in the standby mode and
its power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
Deep Power-Down
When F-RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, F-RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
Automatic Power-Saving (APS)
The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or F-CE# isn't
changed more than 200ns after the last alternation. The
power consumption becomes the same as the stand-by
mode. While in this mode, the output data is latched and can
be read out. New data is read out correctly when addresses
are changed.
4 Apr. 1999 , Rev.1.7

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M6MGT166S4BWG 전자부품, 판매, 대치품
MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
BUS OPERATIONS
Bus Operations for Word-Wide Mode
Mode
Pins
Array
Read
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
Program
Write
Erase
Others
Deep Power Down
F-CE#
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
F-OE#
VIL
VIL
VIL
VIL
VIH
X 2)
VIH
VIH
VIH
X
F-WE#
VIH
VIH
VIH
VIH
VIH
X
VIL
VIL
VIL
X
F-RP#
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
DQ0-15
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
Hi-Z
Command/Data in
Command
Command
Hi-Z
F-RY/BY#
VOH (Hi-Z)
X 1)
X
VOH (Hi-Z)
X
X
X
X
X
VOH (Hi-Z)
1) X at F-RY/BY# is VOL or VOH(Hi-Z).
*The F-RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation.
A pull-up resistor of 10K-100K Ohms is required to allow the F-RY/BY# signal to transition high indicating a Ready WSM condition.
2) X can be VIH or VIL for control pins.
7 Apr. 1999 , Rev.1.7

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M6MGT166S4BWG

CMOS 3.3V-ONLY FLASH MEMORY & CMOS SRAM Stacked-CSP

Mitsubishi
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